////////////////////////////////////////////////////////// application side config file ////////////////////////////////////////////////////// /* * Copyright 2008 * Texas Instruments Incorporated * * All rights reserved. Property of Texas Instruments Incorporated * Restricted rights to use, duplicate or disclose this code are * granted through contract. * */ /* * ======== ceapp.cfg ======== */ /* use the tracing utility module */ var TraceUtil = xdc.useModule('ti.sdo.ce.utils.trace.TraceUtil'); //TraceUtil.attrs = TraceUtil.SOCRATES_TRACING; /* use and configure the osal. */ var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global'); osalGlobal.runtimeEnv = osalGlobal.DSPLINK_LINUX; /* * ======== Engine Configuration ======== */ var Engine = xdc.useModule('ti.sdo.ce.Engine'); var myEngine = Engine.createFromServer( "exe_ser", // Engine name (as referred to in the C app) "./exe_ser.x64P", // path to server exe, relative to its package dir "ti.sdo.ce.examples.servers.exe_ser.evm3530" // server package ); /* * @(#) ti.sdo.ce.examples.apps.video_copy.dualcpu.evm3530; 1, 0, 0,49; 9-11-2008 13:26:52; /db/atree/library/trees/ce-i24x/src/ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////// server side tcf file ////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /* * Copyright 2008 by Texas Instruments Incorporated. * * All rights reserved. Property of Texas Instruments Incorporated. * Restricted rights to use, duplicate or disclose this code are * granted through contract. * */ /* use the all_codecs's TCF file since the BIOS configuration needed for * the two example servers is identical; if you want to have different BIOS * configuration, copy the all_codecs' TCF file over this file. */ //utils.importFile( "../../all_codecs/all.tcf" ); /* * @(#) ti.sdo.ce.examples.servers.video_copy.evm3530; 1, 0, 0,49; 9-11-2008 13:32:33; /db/atree/library/trees/ce-i24x/src/ */ /* * Copyright 2008 * Texas Instruments Incorporated * * All rights reserved. Property of Texas Instruments Incorporated * Restricted rights to use, duplicate or disclose this code are * granted through contract. * */ //var platform = environment["config.platform"]; //print("platform = " + platform); //var platShortName = platform.match(/[^\.]+$/)[0]; /* load platform and device specific configuration parameters */ utils.importFile("exe_evm3530.tci"); /* =========================================================================== * GBL * =========================================================================== */ /* set MAR register to cache external memory 0x80000000-0x8FFFFFFF */ //prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff; //prog.module("GBL").C64PLUSMAR128to159 = 0x0000ff3f; prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffdf; prog.module("GBL").ENABLEALLTRC = false; prog.module("GBL").PROCID = 0; /* =========================================================================== * MEM : startup and SWI stack size * =========================================================================== */ //prog.module("MEM").STACKSIZE = 0x1000; prog.module("MEM").STACKSIZE = 0x400; /* =========================================================================== * Global Settings * =========================================================================== */ prog.module("MEM").ARGSSIZE = 256; //prog.module("MEM").USERCOMMANDFILE = 1; /* =========================================================================== * Enable MSGQ and POOL Managers * =========================================================================== */ bios.MSGQ.ENABLEMSGQ = true; bios.POOL.ENABLEPOOL = true; /* =========================================================================== * Set all code and data sections to use DDR2 * =========================================================================== */ bios.setMemCodeSections (prog, bios.DDR2); //prog.get("IRAM") //bios.DDR2 bios.setMemDataNoHeapSections (prog, bios.DDR2); bios.setMemDataHeapSections (prog, bios.DDR2); /* =========================================================================== * MEM : Global * =========================================================================== */ prog.module("MEM").BIOSOBJSEG = bios.DDR2; prog.module("MEM").MALLOCSEG = bios.DDR2; /* =========================================================================== * TSK : Global * =========================================================================== */ //prog.module("TSK").STACKSEG = bios.L1DSRAM; prog.module("MEM").STACKSEG = bios.L1DSRAM; /* =========================================================================== * Generate configuration files... * =========================================================================== */ if (config.hasReportedError == false) { prog.gen(); } /* * @(#) ti.sdo.ce.examples.servers.all_codecs; 1, 0, 0,137; 9-11-2008 13:31:48; /db/atree/library/trees/ce-i24x/src/ */ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////// server side tci file ////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// /* * Copyright 2008 by Texas Instruments Incorporated. * * All rights reserved. Property of Texas Instruments Incorporated. * Restricted rights to use, duplicate or disclose this code are * granted through contract. * */ /* * Setup platform-specific memory map: */ var mem_ext = [ { comment: "DDR2: off-chip memory for application code and data", name: "DDR2", base: 0x84000000, len: 0x01000000, // 16 MB cached region space: "code/data" }, /*{ comment: "DDR4: off-chip memory for application code and data", name: "DDR4", base: 0x85000000, len: 0x01000000, // 16 MB not used as of now space: "code/data" },*/ { comment: "DDR3: off-chip memory for application code and data", name: "DDR3", base: 0x85000000, len: 0x01000000, // 16 MB non cached region space: "code/data" }, { comment: "DDRALGHEAP: off-chip memory for dynamic algmem allocation", name: "DDRALGHEAP", base: 0x87600000, len: 0x00800000, // 8 MB space: "code/data" }, { comment: "DSPLINK: off-chip memory reserved for DSPLINK code and data", name: "DSPLINKMEM", base: 0x87E00000, len: 0x00100000, // 1 MB space: "code/data" }, { comment: "RESET_VECTOR: off-chip memory for the reset vector table", name: "RESET_VECTOR", base: 0x87F00000, len: 0x00001000, // 4 KB space: "code/data" }, { comment: "L4CORE: L4-Core Interconnect Address Space", name: "L4CORE", base: 0x48000000, len: 0x01000000, // 16 MB space: "data" }, { comment: "L4PER: L4-Peripheral Interconnect Address Space", name: "L4PER", base: 0x49000000, len: 0x00100000, // 1 MB space: "data" }, ]; /* * Internal memory partitioning for evm3530 * * On the left in the diagram below is the layout of internal memory * available on OMAP3530 for data caching and RAM; on the right is the * diagram showing how this configuration file partitions the available * memory. (The 32K for program cache is not affected by this configuration.) * Please find more specifics on how the configuration is done further below. * * * Internal memory on OMAP3430/3530 Memory partitioning in this tcf * * |//////////| |//////////| * 0x107F 8000 +----------+ 0x107F 8000 +----------+ * | | | | * | L2 RAM | 32KB | L2 RAM | 32KB * | | | | * 0x1080 0000 +----------+ 0x1080 0000 +----------+ * | | | | * | L2 | | L2 | * | | 64KB | | 64KB * |RAM/Cache | | Cache | * | | | | * | | | | * 0x1080 FFFF +----------+ 0x1080 FFFF +----------+ * |//////////| |//////////| * : : : : * |//////////| |//////////| * 0x10E0 0000 +----------+ 0x10E0 0000 +----------+ * | L1P | | L1P | * | | 32KB | | 32KB * |RAM/Cache | | Cache | * 0x10E0 7FFF +----------+ 0x10E0 7FFF +----------+ * |//////////| |//////////| * : : : : * |//////////| |//////////| * 0x10F0 4000 +----------+ 0x10F0 4000 +----------+ * | | | | * | L1D RAM | 48KB | L1DSRAM | 48KB * | | | | * | | | | * 0x10F1 0000 +----------+ 0x10F1 0000 +----------+ * | L1D | | L1D | * | | 32KB | | 32KB * |RAM/Cache | | Cache | * 0x10F1 7FFF +- - - - - + 0x10F1 7FFF +- - - - - + * |//////////| |//////////| */ /* * Configure L1D Cache and L1DSRAM segment: l1DMode * * OMAP3530 device has 48KB of physical memory at 0x10F04000 available * as internal RAM, called the "L1DSRAM" segment in BIOS, and it has * another adjacent 32KB at 0x10F10000 that can either be used entirely * for L1D cache, or split between L1D cache and more internal memory. * * The 80KB segment (48KB + 32KB) starts at 0x10F04000. When powered on, * the device uses the upper 32K for L1D cache entirely, so BIOS by default * defines the L1DSRAM segment to be 48KB long and does not change the cache. * * We can change the default behavior, by shrinking the L1D cache and adding * the extra space to L1DSRAM. We can set the L1D cache to be 32K (the default) * or 16K, 8K, 4K, or 0K. The corresponding L1DSRAM sizes then are 48K (the * default), or 64K, 72K, 76K, or 80K. * * The L1DSRAM segment always starts at 0x10F04000. * * Configure L2 Cache memory settings: l2Mode * * This value indicates how the physical internal memory of size 64KB * starting at 0x10800000 will be split between L2 cache and a * general-purpose internal memory segment IRAM. * * The options for l2Mode are: * * "0k" -- IRAM : start = 0x10800000, len = 64KB * L2 Cache: none * "32k" -- IRAM : start = 0x10800000, len = 32KB * L2 Cache: start = 0x10808000, len = 32KB * "64k" -- IRAM : none * L2 Cache: start = 0x10800000, len = 64KB */ var device_regs = { l1PMode: "32k", l1DMode: "32k", l2Mode: "64k" }; var params = { clockRate: 330, catalogName: "ti.catalog.c6000", deviceName: "3530", regs: device_regs, mem: mem_ext }; /* * Now customize the generic platform with parameters specified above. */ utils.loadPlatform("ti.platforms.generic", params); /* =========================================================================== * Enable heaps and tasks * =========================================================================== */ bios.enableMemoryHeaps(prog); bios.enableTskManager(prog); /* =========================================================================== * Create heaps in memory segments that are to have heap * =========================================================================== */ bios.DDR2.createHeap = true; bios.DDR2.heapSize = 0x20000; // 128K bios.DDRALGHEAP.createHeap = true; bios.DDRALGHEAP.heapSize = bios.DDRALGHEAP.len; bios.L1DSRAM.createHeap = true; bios.L1DSRAM.enableHeapLabel = true; bios.L1DSRAM["heapLabel"] = prog.extern("L1DHEAP"); /* * @(#) ti.sdo.ce.examples.servers.all_codecs; 1, 0, 0,137; 9-11-2008 13:31:48; /db/atree/library/trees/ce-i24x/src/ */ //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////