extern EDMA3_DRV_Handle hEdma[]; extern const unsigned int numEdma3Instances; EDMA3_DRV_Result edmaResult = EDMA3_DRV_SOK; unsigned int edma3Id; #pragma DATA_ALIGN(data_in,8); #pragma DATA_ALIGN(data_outa,8); #pragma DATA_ALIGN(data_outb,8); uint32_t data_outa[96]; uint32_t data_outb[48]; static int16_t sinetable[48] = { 0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b, 0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef, 0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4, 0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75, 0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1, 0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c }; int a; void AUDIO_audio_out (unsigned int tcc, EDMA3_RM_TccStatus status, void *appData) { (void)tcc; (void)appData; switch (status) { case EDMA3_RM_XFER_COMPLETE: // restart EDMA3_DRV_enableTransfer (hEdma[0], chtxId,EDMA3_DRV_TRIG_MODE_EVENT); a++; break; case EDMA3_RM_E_CC_DMA_EVT_MISS: break; case EDMA3_RM_E_CC_QDMA_EVT_MISS: break; default: break; } } void AUDIO_Setup_DMA(void) { EDMA3_DRV_PaRAMRegs paramSet_tx = {0,0,0,0,0,0,0,0,0,0,0,0}; unsigned int chtxId1 = 0; unsigned int chtxId2 = 0; unsigned int tcctx = 0; int i,index; unsigned int count; unsigned int numenabled = 0; unsigned int BRCnt = 0; int srcbidx = 0, desbidx = 0; int srccidx = 0, descidx = 0; unsigned int acnt,bcnt,ccnt; /* Initialize EDMA3 first */ edmaResult = edma3init(); if (edmaResult != EDMA3_DRV_SOK) printf("\nEDMA3 Initialization FAILED, error code: %d\n", edmaResult); else printf("\nEDMA3 Initialization PASSED\n"); /* Setup for Channel tx */ tcctx = EDMA3_DRV_TCC_ANY; chtxId = EDMA3_DRV_DMA_CHANNEL_MCASP0_TX; if (edmaResult == EDMA3_DRV_SOK) { edmaResult = EDMA3_DRV_requestChannel (hEdma[0], &chtxId, &tcctx, (EDMA3_RM_EventQueue)0, &AUDIO_audio_out, NULL); } // for two link channels chtxId1 = EDMA3_DRV_LINK_CHANNEL; chtxId2 = EDMA3_DRV_LINK_CHANNEL; if (edmaResult == EDMA3_DRV_SOK) { edmaResult = ( (EDMA3_DRV_requestChannel (hEdma[0], &chtxId1, NULL, (EDMA3_RM_EventQueue)0, &AUDIO_audio_out, NULL)) || (EDMA3_DRV_requestChannel (hEdma[0], &chtxId2, NULL, (EDMA3_RM_EventQueue)0, &AUDIO_audio_out, NULL)) ); } if (edmaResult == EDMA3_DRV_SOK) { /* Fill the PaRAM Set with transfer specific information */ paramSet_tx.srcAddr = (unsigned int)(data_outa); paramSet_tx.destAddr = (unsigned int)(MCASP_DMA_PORT); paramSet_tx.srcBIdx = 1; paramSet_tx.destBIdx = 0; paramSet_tx.srcCIdx = 0; paramSet_tx.destCIdx = 0; paramSet_tx.aCnt = 1; paramSet_tx.bCnt = 48; paramSet_tx.cCnt = 1; paramSet_tx.bCntReload = 48; paramSet_tx.linkAddr = 0xFFFFu; /* Reset opt field first */ paramSet_tx.opt = 0x0u; // Set the TCC paramSet_tx.opt |= ((tcctx << OPT_TCC_SHIFT) & OPT_TCC_MASK); // Set AB synch mode paramSet_tx.opt |= (1 << OPT_SYNCDIM_SHIFT); /* Enable Final transfer completion interrupt */ //paramSet_rx1.opt |= (1 << OPT_ITCINTEN_SHIFT); //paramSet_tx.opt |= (1 << OPT_TCINTEN_SHIFT); /* Now, write the PaRAM Set to the master and first link */ edmaResult = (EDMA3_DRV_setPaRAM (hEdma[0], chtxId, ¶mSet_tx) | EDMA3_DRV_setPaRAM (hEdma[0], chtxId1, ¶mSet_tx)); } if (edmaResult == EDMA3_DRV_SOK) { // modify the source buffer for the second set paramSet_tx.srcAddr = (unsigned int)(data_outb); /* Now, write the PaRAM Set to the second link */ edmaResult = EDMA3_DRV_setPaRAM (hEdma[0], chtxId2, ¶mSet_tx); } // link them if (edmaResult == EDMA3_DRV_SOK) { edmaResult = ( (EDMA3_DRV_linkChannel (hEdma[0], chtxId, chtxId2)) || (EDMA3_DRV_linkChannel (hEdma[0], chtxId1, chtxId2)) || (EDMA3_DRV_linkChannel (hEdma[0], chtxId2, chtxId1)) ); } // fill the two buffers with test sine wave for (i=0;i<48;i++) { data_outa[i*2] = ((sinetable[i] << 15) | 0x00000000); data_outa[(i*2)+1] = ((sinetable[i] << 15) | 0x00000000); data_outb[i*2] = ((sinetable[i+24] << 15) | 0x00000000); data_outb[(i*2)+1] =((sinetable[i+24] << 15) | 0x00000000); } // trigger if (edmaResult == EDMA3_DRV_SOK) { edmaResult = EDMA3_DRV_enableTransfer (hEdma[0], chtxId, EDMA3_DRV_TRIG_MODE_EVENT); } } uint32_t AudioThread(void) { uint32_t rtn = ERR_NO_ERROR; int16_t msec, sec; int16_t sample; rtn = AIC3106_init(); // default initialisation if (rtn != ERR_NO_ERROR) { printf("error initializing aic3106!\r\n"); return (rtn); } rtn = MCASP_init(); // default initialisation if (rtn != ERR_NO_ERROR) { printf("error initializing mcasp!\r\n"); return (rtn); } // No FIFO's (default) // 32 bit slot //SETBIT(MCASP->XFMT,XSSZ_32BITS); // DMA must have XBUSEL off CLRBIT(MCASP->XFMT,BUSEL); // enable the audio clocks, verifying each bit is properly set. SETBIT(MCASP->XGBLCTL, XHCLKRST); while (!CHKBIT(MCASP->XGBLCTL, XHCLKRST)) {} SETBIT(MCASP->RGBLCTL, RHCLKRST); while (!CHKBIT(MCASP->RGBLCTL, RHCLKRST)) {} SETBIT(MCASP->XGBLCTL, XCLKRST); while (!CHKBIT(MCASP->XGBLCTL, XCLKRST)) {} SETBIT(MCASP->RGBLCTL, RCLKRST); while (!CHKBIT(MCASP->RGBLCTL, RCLKRST)) {} SETBIT(MCASP->XINTCTL, RDATA); while (!CHKBIT(MCASP->XINTCTL, RDATA)) {} // Setup and trigger the DMA AUDIO_Setup_DMA(); // Clear transmitter and receiver status MCASP->XSTAT = 0xffff; MCASP->RSTAT = 0xffff; // take serializers out of reset SETBIT(MCASP->XGBLCTL, XSRCLR); while (!CHKBIT(MCASP->XGBLCTL, XSRCLR)) {} SETBIT(MCASP->RGBLCTL, RSRCLR); while (!CHKBIT(MCASP->RGBLCTL, RSRCLR)) {} // isr will now suddenly start servicing the queue - wait for clear //while (!CHKBIT(MCASP->XSTAT,XDATA)) {} /* Write a 0, so that no underrun occurs after releasing the state machine */ //MCASP->XBUF11 = 0; SETBIT(MCASP->XGBLCTL, XSMRST); while (!CHKBIT(MCASP->XGBLCTL, XSMRST)) {} SETBIT(MCASP->RGBLCTL, RSMRST); while (!CHKBIT(MCASP->RGBLCTL, RSMRST)) {} SETBIT(MCASP->XGBLCTL, XFRST); while (!CHKBIT(MCASP->XGBLCTL, XFRST)) {} SETBIT(MCASP->RGBLCTL, RFRST); while (!CHKBIT(MCASP->RGBLCTL, RFRST)) {} // wait for transmit ready and send a dummy byte. // // while(!CHKBIT(MCASP->SRCTL11, XRDY)) {} //MCASP->XBUF11 = 0; // trigger tx event usinf the DMA ESR register //SETBIT(EDMA3_0_GLOB_CHAN_REG->ESR,EDMA3_DRV_DMA_CHANNEL_MCASP0_TX); a=0; /* // transmit beep. for (sec = 0; sec < 5; sec++) { for (msec = 0; msec < 1000; msec++) { for (sample = 0; sample < 48; sample++) { // wait for xmit ready and send a sample to the left channel. while (!CHKBIT(MCASP->SRCTL11, XRDY)) {} MCASP->XBUF11 = (sinetable[sample] << 15) | 0x00000000; // wait for xmit ready and send a sample to the left channel. while (!CHKBIT(MCASP->SRCTL11, XRDY)) {} MCASP->XBUF11 = (sinetable[sample] << 15) | 0x00000000; } } } */ // while (1) {;} return rtn; }