/*
 *  Copyright 2008 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *
 *  @(#) DSP/BIOS_Examples 5,3,3 09-23-2008 (biosEx-j03)
 */
/*
 *  ======== Main.tcf ========
 *  Configuration script used to generate the example's configuration files
 */

/*
 *  Load the evm6474 settings that are common to most examples.
 */

utils.loadPlatform("ti.platforms.evm6474");

/*
 *  Import the bios settings that are common to evm6474.
 */

utils.importFile("evm6474_common.tci");

/*
 *  Import the Main configuration settings that apply to all platforms.
 */

utils.importFile("main.tci");

bios.POOL.ENABLEPOOL = 0;
bios.POOL.ENABLEPOOL = 1;
bios.MEM.instance("CACHE_L1D").destroy();
bios.MEM.instance("CACHE_L1P").destroy();
bios.MEM.instance("DDR2").destroy();
bios.MEM.USERCOMMANDFILE = 1;
bios.HWI.instance("HWI_INT4").fxn = prog.extern("HWI_Vijay", "asm");
bios.HWI.instance("HWI_INT4").interruptSelectNumber = 76;
bios.HWI.instance("HWI_INT4").fxn = prog.extern("HWI_IPC", "asm");
bios.HWI.instance("HWI_INT4").fxn = prog.extern("HWI_IPC");
bios.HWI.instance("HWI_INT4").useDispatcher = 1;
bios.HWI.instance("HWI_INT4").fxn = prog.extern("is_IPC");
bios.MEM.USERCOMMANDFILE = 0;
bios.MEM.ENABLELOADADDR = 0;
bios.MEM.USERCOMMANDFILE = 1;
bios.POOL.ENABLEPOOL = 0;
bios.MEM.STACKSIZE = 0x1000;
bios.MEM.STACKSIZE = 0x100000;
bios.MEM.STACKSIZE = 0xffff;
bios.GBL.C64PLUSL1PCFG = "0k";
bios.GBL.C64PLUSL1DCFG = "0k";
bios.MSGQ.ENABLEMSGQ = 0;
bios.HWI.instance("HWI_INT4").useDispatcher = 1;
bios.MEM.STACKSIZE = 0x1ffff;
bios.MEM.BIOSOBJSEG = prog.get("L2RAM");
bios.MEM.instance("L2RAM").heapSize = 0x00005000;
bios.MEM.instance("L2RAM").heapSize = 0x00006000;
bios.MEM.instance("L2RAM").heapSize = 0x00008000;
bios.MEM.instance("L2RAM").heapSize = 0x00018000;
bios.MEM.instance("L2RAM").heapSize = 0x00008000;
bios.MEM.instance("L2RAM").heapSize = 0x00020000;
bios.TSK.STACKSIZE = 8192;
bios.TSK.STACKSIZE = 2048;
bios.TSK.STACKSIZE = 1024;
bios.MEM.instance("L2RAM").len = 0x00080000;
bios.MEM.instance("L2RAM").len = 0x00100000;
bios.MEM.instance("L2RAM").heapSize = 0x00030000;
bios.MEM.instance("L2RAM").heapSize = 0x00006000;
bios.GBL.C64PLUSL1PCFG = "32k";
bios.GBL.C64PLUSL1DCFG = "32k";
bios.GBL.C64PLUSL2CFG = "64k";
bios.MEM.instance("CACHE_L2").destroy();
bios.MEM.instance("L2RAM").heapSize = 0x00008000;
bios.MEM.instance("L2RAM").heapSize = 0x00020000;
bios.MEM.instance("L2RAM").heapSize = 0x00010000;
bios.MEM.instance("L2RAM").len = 0x00200000;
bios.MEM.instance("L2RAM").len = 0x00100000;
bios.MEM.instance("L2RAM").heapSize = 0x00020000;
bios.MEM.instance("L2RAM").heapSize = 0x00030000;
bios.MEM.instance("L2RAM").heapSize = 0x00040000;
bios.MEM.create("L1D_RAM");
bios.MEM.instance("L1D_RAM").base = 0x00f04000;
bios.MEM.instance("L1D_RAM").len = 0x0000c000;
bios.MEM.instance("L1D_RAM").createHeap = 0;
bios.GBL.C64PLUSL2CFG = "256k";
bios.MEM.create("DDR_LOG");
bios.MEM.instance("DDR_LOG").destroy();
bios.MEM.instance("L1D_RAM").len = 0x00008000;
bios.MEM.create("C1_DDR_DATA_RAM");
bios.MEM.create("C1_DDR_PROG_RAM");
bios.MEM.instance("C1_DDR_DATA_RAM").comment = "DATA RAM";
bios.MEM.instance("C1_DDR_DATA_RAM").base = 0x08500000;
bios.MEM.instance("C1_DDR_DATA_RAM").len = 0x02000000;
bios.MEM.instance("C1_DDR_DATA_RAM").createHeap = 0;
bios.MEM.instance("C1_DDR_PROG_RAM").comment = "PROG RAM";
bios.MEM.instance("C1_DDR_PROG_RAM").base = 0x87000000;
bios.MEM.instance("C1_DDR_PROG_RAM").len = 0x02000000;
bios.MEM.instance("C1_DDR_PROG_RAM").createHeap = 0;
bios.MEM.instance("C1_DDR_PROG_RAM").space = "code";
bios.MEM.create("CMN_DDR_DATA_RAM");
bios.MEM.instance("CMN_DDR_DATA_RAM").createHeap = 0;
bios.MEM.instance("CMN_DDR_DATA_RAM").comment = "DATA RAM";
bios.MEM.instance("CMN_DDR_DATA_RAM").base = 0x80000000;
bios.MEM.instance("CMN_DDR_DATA_RAM").len = 0x01000000;
bios.LOG.create("fatal");
bios.LOG.instance("trace").bufSeg = prog.get("CMN_DDR_DATA_RAM");
bios.LOG.instance("trace").bufLen = 1024;
bios.LOG.instance("fatal").bufSeg = prog.get("CMN_DDR_DATA_RAM");
bios.LOG.instance("fatal").bufLen = 1024;
bios.LOG.create("warning");
bios.LOG.instance("warning").bufSeg = prog.get("CMN_DDR_DATA_RAM");
bios.LOG.instance("warning").bufLen = 1024;
bios.LOG.create("event");
bios.LOG.instance("event").bufLen = 1024;
bios.LOG.instance("event").bufSeg = prog.get("CMN_DDR_DATA_RAM");
bios.MEM.create("C0_DDR_DATA_RAM");
bios.MEM.instance("C0_DDR_DATA_RAM").comment = "DATA RAM";
bios.MEM.instance("C0_DDR_DATA_RAM").len = 0x02000000;
bios.MEM.instance("C0_DDR_DATA_RAM").base = 0x08500000;
bios.MEM.instance("C0_DDR_DATA_RAM").createHeap = 0;
bios.MEM.instance("C0_DDR_DATA_RAM").base = 0x81000000;
bios.MEM.instance("C1_DDR_DATA_RAM").base = 0x85000000;
bios.MEM.create("C0_DDR_PROG_RAM");
bios.MEM.instance("C0_DDR_PROG_RAM").comment = "PROG RAM";
bios.MEM.instance("C0_DDR_PROG_RAM").len = 0x02000000;
bios.MEM.instance("C0_DDR_PROG_RAM").base = 0x87000000;
bios.MEM.instance("C0_DDR_PROG_RAM").createHeap = 0;
bios.MEM.instance("C0_DDR_PROG_RAM").base = 0x83000000;
bios.MEM.create("C2_DDR_DATA_RAM");
bios.MEM.instance("C2_DDR_DATA_RAM").comment = "DATA RAM";
bios.MEM.instance("C2_DDR_DATA_RAM").len = 0x02000000;
bios.MEM.instance("C2_DDR_DATA_RAM").base = 0x81000000;
bios.MEM.instance("C2_DDR_DATA_RAM").createHeap = 0;
bios.MEM.instance("C2_DDR_DATA_RAM").base = 0x89000000;
bios.MEM.create("C2_DDR_PROG_RAM");
bios.MEM.instance("C2_DDR_PROG_RAM").comment = "DATA RAM";
bios.MEM.instance("C2_DDR_PROG_RAM").len = 0x02000000;
bios.MEM.instance("C2_DDR_PROG_RAM").base = 0x81000000;
bios.MEM.instance("C2_DDR_PROG_RAM").createHeap = 0;
bios.MEM.instance("C2_DDR_PROG_RAM").base = 0x8b000000;
bios.LOG.instance("fatal").bufLen = 4096;
bios.LOG.instance("trace").bufLen = 4096;
bios.LOG.instance("warning").bufLen = 4096;
bios.GBL.C64PLUSL2CFG = "0k";
bios.PRD.USECLK = 0;
bios.MEM.STACKSEG = prog.get("C0_DDR_DATA_RAM");
bios.MEM.STACKSIZE = 0xfffff;
bios.PRD.USECLK = 1;
bios.MEM.STACKSIZE = 0xffffff;
bios.MEM.STACKSIZE = 0x1ffff;
bios.MEM.STACKSEG = prog.get("L2RAM");
bios.PRD.USECLK = 0;
bios.PRD.USECLK = 1;
bios.PRD.USECLK = 0;
bios.PRD.USECLK = 1;
bios.MEM.STACKSIZE = 0xffffff;
bios.MEM.STACKSEG = prog.get("C0_DDR_DATA_RAM");
bios.MEM.STACKSIZE = 0x1ffff;
bios.MEM.STACKSEG = prog.get("L2RAM");
bios.PRD.USECLK = 0;
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!

if (config.hasReportedError == false) {
    prog.gen();
}