/* * This GEL file (init6x0x.gel) is loaded on the command line * of Code Composer. It provides example code on how to * reset the C6x DSP and initialize the External Memory Interface. * * You may have to edit settings in emif_init() to your own * specifications as the example is applicable to the C6x EVM. * */ /* ; Aux DMA Control Register Fields: ; bits (0:3): DMD Channel Priority, set to 1 to configure DMA ; channels priority from highest priority to lowest ; priority as follows: DMA_0, DMA_AUX, DMA_1, DMA_2, DMA_3. ; ; bits (4): Auxiliary Channel Priority Mode, set to 1 to give ; the Aux DMA channel higher priority than the CPU. */ /* CE1 EMIF_CE1_CTRL_INIT_VAL .set 0xF61FD811 ;16-bit ROM ;rd,wr setup = 15 CLK1 ;rd,wr hold = 1 CLK1 ;rd,wr stobe = 24 CLK1 ;TA = 3 CLK1 */ /* CE0 EMIF_CE0_CTRL_INIT_VAL .set 0x00000030 ;CE0 Space is SDRAM */ #define DMA_AUX_CTL_REG_INIT_VAL 0x00000011 #define EMIF_GCTRL_INIT_VAL 0x00000079 /* #define EMIF_CE1_CTRL_INIT_VAL 0xF61FD811 */ #define EMIF_CE1_CTRL_INIT_VAL 0x00000030 #define EMIF_CE0_CTRL_INIT_VAL 0x00000030 /*---------------------------------------------------------------------------*/ /* EMIF REGISTER VALUES FROM SPRU269B */ /*---------------------------------------------------------------------------*/ #define EMIF_GCTL 0x01800000 #define EMIF_CE1 0x01800004 #define EMIF_CE0 0x01800008 #define EMIF_CE2 0x01800010 #define EMIF_CE3 0x01800014 #define EMIF_SDRAMCTL 0x01800018 #define EMIF_SDRAMREF 0x0180001c #define EMIF_GCTRL_ADDR 0x01800000 #define EMIF_CE0_CTRL_ADDR 0x01800008 #define EMIF_CE1_CTRL_ADDR 0x01800004 #define EMIF_CE2_CTRL_ADDR 0x01800010 #define EMIF_CE3_CTRL_ADDR 0x01800014 #define EMIF_SDRAM_CTRL_ADDR 0x01800018 #define EMIF_SDRAM_REFRESH_ADDR 0x0180001C #define DMA_AUX_CTL_REG 0x01840070 #define CSR_LOCATION 0x00010300 /**********************************************************************/ /* External Memory Interface Contrl Registers */ /**********************************************************************/ #define EMIF_GCTRL_ADDR 0x01800000 #define EMIF_CE0_CTRL_ADDR 0x01800008 #define EMIF_CE1_CTRL_ADDR 0x01800004 #define EMIF_CE2_CTRL_ADDR 0x01800010 #define EMIF_CE3_CTRL_ADDR 0x01800014 #define EMIF_SDRAM_CTRL_ADDR 0x01800018 #define EMIF_SDRAM_REFRESH_ADDR 0x0180001C /***********************************************************************/ /* Timer registers */ /***********************************************************************/ #define TIMER_CONTROL_ADDR 0x01940000 #define TIMER_PERIOD_ADDR 0x01940004 #define TIMER_COUNTER_ADDR 0x01940008 #define TIMER1_CONTROL_ADDR 0x01980000 #define TIMER1_PERIOD_ADDR 0x01980004 #define TIMER1_COUNTER_ADDR 0x01980008 /* #define TIMER_CONTROL ( (UINT32 *) TIMER_CONTROL_ADDR ) #define TIMER_PERIOD ( (UINT32 *) TIMER_PERIOD_ADDR ) #define TIMER_COUNTER ( (UINT32 *) TIMER_COUNTER_ADDR ) #define TIMER1_CONTROL ( (UINT32 *) TIMER1_CONTROL_ADDR ) #define TIMER1_PERIOD ( (UINT32 *) TIMER1_PERIOD_ADDR ) #define TIMER1_COUNTER ( (UINT32 *) TIMER1_COUNTER_ADDR ) */ menuitem "ConfigureForSimOrEmul"; hotmenu InitForSimOrEmul() { General_Init(); } menuitem "Memory Map"; hotmenu Set_Memory_Map() { setup_memory_map(); } hotmenu Clear_Memory_Map() { clear_memory_map(); } setup_memory_map() { /* enable the memory map feature in Code Composer Studio */ GEL_MapOn(); /* start out by resetting all memory to unreadable and unwritable */ GEL_MapReset(); /* the syntax for GEL_MapAdd(address, page, length, readable, writeable) * page: Program Memory = 0, Data Memory = 1, I/O Space = 2 * readable: Not Readable = 0, Readable = 1 * writeable: Not Writeable = 0, Writeable = 1 */ // GEL_MapAdd(0x00000000, 0, 0x00010000, 1, 1); // Program Mem /* GEL_MapAdd(0x00400000, 0, 0x00100000, 1, 0);*/ // Data page // GEL_MapAdd(0x00010000, 0, 0x10000, 1, 1); // Test Area // GEL_MapAdd(0x00400000, 0, 0x10000, 1, 1); // GEL_MapAdd(0x00410000, 0, 0x10000, 1, 1); // GEL_MapAdd(0x01400000, 0, 0x00400000, 1, 1); GEL_MapAdd(0x0000000, 0, 0x01800000, 1, 1); GEL_MapAdd(0x01800000,0,0x20,1,1); /* EMIF control registers */ GEL_MapAdd(0x01840000,0,0x74,1,1); /* DMA control registers */ GEL_MapAdd(0x01880000,0,0x4,1,1); /* HPI registers */ GEL_MapAdd(0x018c0000,0,0x28,1,1); /* McBSP0 registers */ GEL_MapAdd(0x01900000,0,0x28,1,1); /* McBSP1 registers */ GEL_MapAdd(0x01940000,0,0xc,1,1); /* Timer0 registers */ GEL_MapAdd(0x01980000,0,0xc,1,1); /* Timer1 registers */ GEL_MapAdd(0x019c0000,0,0xc,1,1); /* Interrupt selector registers */ GEL_MapAdd(0x02000000, 0, 0x01000000, 1, 1); GEL_MapAdd(0x03000000, 0, 0x01000000, 1, 1); } clear_memory_map() { GEL_MapOff(); } /* * The StartUp() function is called every time you start * Code Composer. You can customize this function to * initialize wait states in the EMIF or to perform * other initialization. */ StartUp() { /* C6701 map1 specific memory mapping */ GEL_MapOn(); GEL_MapReset(); setup_memory_map(); } OnTargetConnect() { /* initialize the EMIF registers on the C6x when Code Composer starts up */ emif_init(); } /* OnReset callback function called after the target processor has been reset */ OnReset(int nErrorCode) { if (nErrorCode) { GEL_TextOut("An error occured while resetting -%d-\n",nErrorCode); } else { emif_init(); } } /* * Menuitem creates a selection available beneath the GEL * menu selection in Code Composer Studio. */ menuitem "Resets"; hotmenu Reset_and_EMIF_Setup() { GEL_Reset(); emif_init(); } hotmenu Reset_EMIFset_and_ClearBreakPts() { GEL_Reset(); emif_init(); GEL_BreakPtReset(); } /*********************************************/ emif_init() { /*--------------------------------------------------------------------------*/ /* EMIF REGISTER VALUES FROM SPRU269B */ /*---------------------------------------------------------------------------*/ #define EMIF_GCTL 0x01800000 #define EMIF_CE1 0x01800004 #define EMIF_CE0 0x01800008 #define EMIF_CE2 0x01800010 #define EMIF_CE3 0x01800014 #define EMIF_SDRAMCTL 0x01800018 #define EMIF_SDRAMREF 0x0180001c /*********************************************************** * Edit values below to conform to your specifications * The following assumes the EVM6x memory configuration ***********************************************************/ /* OK for 133, 160 MHK CPU clock rate */ *(int *)EMIF_GCTL = 0x3060; /* CE1 */ *(int *)EMIF_CE1 = 0x40f40323; /* CE0 SBSRAM */ *(int *)EMIF_CE0 = 0x30; /* CE2 and CE3 SBSRAM */ *(int *)EMIF_CE2 = 0x30; *(int *)EMIF_CE3 = 0x30; } General_Init() { DisableInterrupts(); ConfigureDma(); ConfigureTimer1(); /* ConfigureEmif(); */ emif_init(); /* Chip is now ready for Simulation or Emulation*/ } DisableInterrupts() { /* Control Status Register Initialization */ /* CSR register gets: */ /* CSR_INIT_MASK .set 0xFFFFFF1C ;GIE(0) = 0, disable all maskable interrupts ;PGIE(1) = 0, clear previous GIE bit ;PCC(5:7) = 0, cache disabled */ /* #define CSR_INIT_MASK 0xFFFFFF1C; *(int *)CSR_LOCATION = CSR_INIT_MASK; */ } ConfigureDma() { *(int *)DMA_AUX_CTL_REG = DMA_AUX_CTL_REG_INIT_VAL; } ConfigureTimer1() { /* Clear the TOUT, Period */ *(int *)TIMER1_PERIOD_ADDR = 0xFFFFFFFE; *(int *)TIMER1_COUNTER_ADDR = 0xFFFFFFFE; } ConfigureEmif() { *(int *)EMIF_GCTRL_ADDR = EMIF_GCTRL_INIT_VAL; *(int *)EMIF_CE0_CTRL_ADDR = EMIF_CE1_CTRL_INIT_VAL; *(int *)EMIF_CE0_CTRL_ADDR = EMIF_CE0_CTRL_INIT_VAL; /* OK for 133, 160 MHK CPU clock rate */ *(int *)EMIF_GCTL = 0x3060; /* CE2 and CE3 SBSRAM */ *(int *)EMIF_CE2_CTRL_ADDR = 0x30; *(int *)EMIF_CE3_CTRL_ADDR = 0x30; }