/********************************************************************** * Copyright 1999 Siemens Medical Systems, Inc., Ultrasound Group * * All Rights Reserved. * * * * Header: CommonLink.cmd * * Subsystem: SipDsp * * Description: Common Memory Architecture File * * * **********************************************************************/ /* Linker commands */ -heap 0x1000 -stack 0x1000 /********************************************************************** * * Memory Map 1 * * 0 - 003F FFFF 4M, only first 64K usable (Internal PM RAM) * 40 0000 - 013F FFFF 16M, CE0 * 140 0000 - 017F FFFF 4M, CE1 - EPROM * 200 0000 - 02FF FFFF 16M, CE2 * 300 0000 - 03FF FFFF 16M, CE3 * 8000 0000 - 8003 FFFF 4M, only first 64K usable (Internal DM RAM) * **********************************************************************/ MEMORY { /* NOTE !!!!!! */ /* Memory section name is unique only in the first SEVEN characters */ /* */ /****************************************************************************/ /* CE0 Space Memory */ /****************************************************************************/ /******************************************************************/ /* Memory to hold application at run time. To be loaded with */ /* stored in SipFlash EPROM. */ /* SIZE reserved: 1M */ /******************************************************************/ CE0_S1: o = 00400000h, l = 00010000h /* 64K byte - run-address space for */ /* .cinit data and extensive-POST code */ CE0_S2: o = 00410000h, l = 00000200h /* 512; relocated interrupts vector */ CE0_S3: o = 00410200h, l = 000DFDF4h /* application s/w */ /* 1M - 64K -524 */ /* 64K from CE0_S1, CE0_S1a */ /* 524 from CE0_S2, CE0_S3a, CE0_S3b */ CE0_S3a: o = 004FFFF4h, l = 00000008h /* 4, BE Brd ID, SwVersionNumber */ CE0_S3b: o = 004FFFFCh, l = 00000004h /* 4, Checksum */ /******************************************************************/ /* CE0_S4's - Data Storage for table, Luts etc ... */ /* SIZE reserved: 2.5 M */ /* */ /* Bottom 64K bytes is reserved for test parameters as follows: */ /* */ /* 0x770000 - Doppler test params; DUI s/w expects this address */ /* TBD ... */ /* */ /* */ /******************************************************************/ CE0_S4: o = 00500000h, l = 00270000h /* 2.5M - 64K */ CE0_S4a: o = 00770000h, l = 00005000h /* 20K, Dedicated to */ /* Doppler Test params*/ /* other sections go here */ CE0_S4z o = 00775000h, l = 0000B000h /* 44K, Dedicated to */ /* Test params */ /******************************************************************/ /* CE0S5's - Memory set aside for communications to external */ /* devices like SIP-FPGA, CPU ... */ /* SIZE reserved: 0.5M */ /******************************************************************/ CE0_S5a: o = 00780000h, l = 00001000h /* 4K, Ipc Shared Mem */ CE0_S5b: o = 00781000h, l = 00000004h /* 4, fpgaToDspIset */ CE0_S5c: o = 00781004h, l = 00000004h /* 4, dspToFpgaIset */ CE0_S5d: o = 00781008h, l = 00000004h /* 4, ipcMailBox */ CE0_S5e: o = 0078100Ch, l = 00000800h /* 2K, DSP addresses accessed by CPU */ CE0_S5f: o = 0078180Ch, l = 00000050h /* 80, Derived WF Ctrl data */ CE0_S5g: o = 0078185Ch, l = 00000004h /* 4, isCineTsCpuDone */ CE0_S5h: o = 00781860h, l = 00000004h /* 4, isPyHwPresent */ CE0_S5i: o = 00781864h, l = 00000004h /* 4, pyHeartRate */ CE0_S5j: o = 00781868h, l = 00000004h /* 4, PHYSIO_WINS_2_3_EN */ /* Next section go here */ /* Reserved for future use */ CE0_S5w: o = 0078186Ch, l = 00002794h /* 12K-6K-2K-108, reserved */ CE0_S5z: o = 00784000h, l = 0007C000h /* 512K - 16K */ /******************************************************************/ /* CE0_S6's - CINE memory */ /* SIZE reserved: 12M */ /******************************************************************/ CE0_S6: o = 00800000h, l = 00C00000h /* 12M */ /****************************************************************************/ /* CE1 Space Memory */ /****************************************************************************/ /* ************ TBD ***********************************************/ /* temp break CE1_S1 into two sections until Cache Mode works */ CE1_S0: o = 01400000h, l = 00000200h /* 512 */ CE1_S1: o = 01400200h, l = 0000EE00h /* 64K - 512 */ CE1_S2: o = 01410000h, l = 00010000h /* .cinit data & extended POST code */ CE1_S3: o = 01420000h, l = 00000200h /* 512, reserved for Interrupt Vectors reallocation */ CE1_S4: o = 01420200h, l = 000DFDF4h /* 1M-128K-524, Application */ CE1_S5: o = 014FFFF4h, l = 00000008h /* 8, BE Brd ID, SwVersionNumber */ CE1_S6: o = 014FFFFCh, l = 00000004h /* 4, CheckSum */ CE1_S7: o = 01500000h, l = 00300000h /* 3M, Not populated */ /****************************************************************************/ /* CE2 Space Memory */ /* */ /* CE3_S1 - SipFpga Inteface info for Signal Input Acquision and Trace */ /* Output Deliver */ /* CE2_S2 - Data Acq Input buffers */ /* CE2_S3 - Trace output buffers and other params */ /* CE2_Z1 - Reserved for outputting debug aids, e.g.: trigger for Logic */ /* Analyzer. */ /****************************************************************************/ CE2_S1: o = 02000000h, l = 00010000h /* 64K */ CE2_S2: o = 02010000h, l = 00400000h /* 4M */ CE2_S3: o = 02410000h, l = 00BEF7FFh /* 16M -64K - 4M - 2K */ /* Reserved last 2K */ /* bytes for use in */ /* adding debugging */ /* parameters */ CE2_Z1: o = 02FFF7FFh, l = 00000800h /* 2K */ /****************************************************************************/ /* CE3 Space Memory */ /* */ /* IMPORTANT NOTE !!!!!!!!!!! */ /* */ /* Due to the problem of Invalid SDRAM Access To Last 1 Kbyte of CE3, the */ /* total size of CE3 will be configured to EXCLUDE the last 1 Kkyte. This */ /* SDRAM problem is reported the TMS320C6701 Silicon Errata Sheets, under */ /* the Revision 1 Silicion Bugs. */ /* */ /* */ /* CE3_S1 - SipFpga Inteface info for Signal Input Acquision and Trace */ /* Output Deliver */ /* CE3_S2 - Data Acq Input buffers */ /* CE3_S3 - Trace output buffers and other params */ /* CE3_Z1 - Reserved to exclude the last 1Kbyte of SDRAM as noted above. */ /* */ /****************************************************************************/ CE3_S1: o = 03000000h, l = 00010000h /* 64K */ CE3_S2: o = 03010000h, l = 00400000h /* 4M */ CE3_S3: o = 03410000h, l = 00BEF7FFh /* 16M -64K - 4M - 2K */ CE3_Z1: o = 03FFF7FFh, l = 00000800h /* 2K */ /****************************************************************************/ /* Internal Data Memory */ /****************************************************************************/ IDM_S1 o = 80000000h, l = 00000024h /* 36, ext POST buffer */ IDM_S2 o = 80000024h, l = 00000020h /* 32, POST status */ IDM_S3 o = 80000048h, l = 00001000h /* 4K, stack, MUST be */ /* All IDM_S4's section total to 2K - (IDM_S1 + IDM_S2) */ IDM_S4a o = 80001048h, l = 00000054h /* DW Control Data */ IDM_S4 o = 8000109Ch, l = 00000564h /* exec Params */ IDM_S5 o = 80001600h, l = 0000EA00h /* 58K app params */ /****************************************************************************/ /* Internal Program Memory */ /****************************************************************************/ ONC_PM0 o = 00000000h, l = 00000200h /* .5 K */ ONC_PM1 o = 00000200h, l = 0000FE00h /* 64K - .5K */ } SECTIONS { /************************************* * Compiler's Uninitialized Sections * *************************************/ .stack > IDM_S3 /* stack (local variables) */ .bss > IDM_S5 /* global and static variables */ EXEC_BSS_DATA > IDM_S5 /* global and static variables */ /* Overlay Mop and Dop */ UNION : > IDM_S5 { DOP_BSS_DATA: /* global and static variables */ MOP_BSS_DATA: /* global and static variables */ } .sysmem > CE0_S4 /* memory for heap */ .cio > CE0_S4 /* buffers for stdio functions */ .far > CE0_S4 /* global and statics declared far */ .const: > CE0_S4 /****************************************** * Uninitialized sections defined by user * ******************************************/ EXEC_FARBSS_DATA > CE0_S4 DOP_FARBSS_DATA > CE0_S4 MOP_FARBSS_DATA > CE0_S4 PY_FARBSS_DATA > CE0_S4 EXEC_FAR_DATA > CE0_S4 DOP_FAR_DATA > CE0_S4 MOP_FAR_DATA > CE0_S4 PY_FAR_DATA > CE0_S4 DP_TEST_BUFFER > CE0_S4a MODTEST_FAR_DATA > CE0_S4z DEBUG_FAR_DATA > CE0_S4z extPostCirBuff > IDM_S1 postParam > IDM_S2 execParam > IDM_S4 .table > CE0_S4 far > CE0_S4 ipcSharedMem > CE0_S5a fpgaToDspIset > CE0_S5b dspToFpgaIset > CE0_S5c ipcMailbox > CE0_S5d dspAddrBuffLoc > CE0_S5e cineTsCpuDone > CE0_S5g isPyHwPresent > CE0_S5h pyHeartRate > CE0_S5i pyWin2Win3En > CE0_S5j dWControlBuff > IDM_S4a relocatedIST > CE0_S2 /* relocated Interrrupt Service Table */ cine > CE0_S6 pingBufferHeader > CE2_S1 piProtectBlk_OFC2 > CE2_S2 piDataInBlk_OFC2 > CE2_S3 pongBufferHeader > CE3_S1 poProtectBlk_OFC3 > CE3_S2 poDataInBlk_OFC3 > CE3_S3 /* Simulation testing related sections */ test > CE2_S3 }