#include "rac_cycle_prediction.h" int main() { printf("Rac Test main Started\n"); return 0; } void TSK_test() { printf("Rac Task main Started\n"); test_main(); printf("Rac Task main Completed\n"); } void rac_test_main() { CSL_FsyncTriggerGenNum evenGenNum; // event gen to force trigger v_u32_t *edma_eesr_reg_ptr;//event enable set register edma_eesr_reg_ptr = (v_u32_t*)(CSL_EDMA3CC_0_REGS + 0x1030); /** Configure FSYNC */ printf("Rac FSYNC Config Started\n"); exec_fsync_cpc_init(); printf("Rac FSYNC Config Completed\n"); exec_aif_init_config(); printf("Rac AIF Completed\n"); /** Setup EDMA Channels */ printf("Rac EDMA3 config Started\n"); exec_rac_edma3_config(); printf("Rac EDMA3 Config Completed\n"); *edma_eesr_reg_ptr = 0x01820000; //events 17 and 23 and 24 } u32_t input1_src_buff[25] ; u32_t input2_src_buff[25] ; u32_t input3_src_buff[25] ; u32_t input4_src_buff[25] ; u32_t rac_debug_src_value = 0xAABBCCDD; u32_t rac_debug_dest_value = 0; void exec_rac_edma3_config() { com_edma_channel_info_t channel; u16_t param_num[4]; CSL_Edma3ParamHandle param_handle; CSL_Edma3ParamSetup param_setup; CSL_Edma3ChannelObj h_edma_obj; CSL_Edma3ChannelHandle h_edma_handle; CSL_Edma3ParamHandle h_edma_param[4]; u32_t link_index=0; u32_t chipint8_cnt=0; u32_t temp_ctr = 0; for(temp_ctr = 0; temp_ctr < 100; temp_ctr++) { input1_src_buff[temp_ctr] = 0x00121200 + temp_ctr; input2_src_buff[temp_ctr] = 0x00121200 + temp_ctr; input3_src_buff[temp_ctr] = 0x00121200 + temp_ctr; input4_src_buff[temp_ctr] = 0x00121200 + temp_ctr; } /** Initialize EDMA module */ com_edma3_module_init(); /** Setup EDMA3 channels for RAC, AIF and FSYNC working */ /** DUMMY INPUT FOR CHANNEL #8*/ channel.param_num = ¶m_num[0]; channel.param_handle = ¶m_handle; channel.channel_obj_ptr = &h_edma_obj; channel.edma_channel_num = 8; channel.num_of_params = 1; channel.param_num[0] = 8; channel.channel_handle = h_edma_handle; channel.param_handle = &h_edma_param[0]; com_edma3_channel_init(&channel); param_setup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, /*Intermediate chaining Enabled*/ CSL_EDMA3_TCCH_DIS,/*Final chaining Enabled*/ CSL_EDMA3_ITCINT_DIS,/*Intermediate Interrupt Disabled*/ CSL_EDMA3_TCINT_DIS, /*Final Interrupt Disabled*/ COM_INVALID_EDMA_CHANNEL,/*No need to Chain To ANY channel*/ CSL_EDMA3_TCC_NORMAL,/* TCC Mode is normal*/ CSL_EDMA3_FIFOWIDTH_NONE, /* FIFO is disabled*/ CSL_EDMA3_STATIC_EN, /* Static option disabled*/ CSL_EDMA3_SYNC_A, /* A-Synchronized Transfer*/ CSL_EDMA3_ADDRMODE_INCR, /* Source in increment mode*/ CSL_EDMA3_ADDRMODE_INCR /* Destination in increment mode*/ ); // param_setup.srcAddr = (u32_t)(&input_src_buff[0] | 0x10000000 );//(u32_t)(gbl_handle_fsync->regs->SYSVAL); /** Source address : SYSTEM Time Register of FSYNC */ param_setup.srcAddr = (u32_t)&(gbl_handle_fsync->regs->SYSVAL); /** Source address : SYSTEM Time Register of FSYNC */ param_setup.aCntbCnt = CSL_EDMA3_CNT_MAKE(sizeof(u32_t),1); /** One U32 value "SYSVAL" */ // param_setup.dstAddr = (u32_t)(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_ANT[0]);//(u32_t)(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_TIME); /** Destination address : Front End Time Register of RAC */ param_setup.dstAddr = (u32_t)&(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_TIME); /** Destination address : Front End Time Register of RAC */ param_setup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(sizeof(CSL_Edma3ParamSetup),0); param_setup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(COM_EDMA_PARAM_OFFSET(EDMA_SRIO_LINK_NULL),0); param_setup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0); param_setup.cCnt = 1; com_edma3_param_setup(&h_edma_param[0], ¶m_setup); /**1st Channel: Channel #23 and PaRAM #: This Channel does Timestamp Transfer from FSYNC to RAC FEI every 32 chips This channel is triggered by FSYNC every 32 chips. FSYNC event used to trigger this channel is CSL_FSYNC_TRIGGER_GEN_11. One timestampt is enough to process all streams in one period.*/ channel.param_num = ¶m_num[0]; channel.param_handle = ¶m_handle; channel.channel_obj_ptr = &h_edma_obj; channel.edma_channel_num = COM_TIMESTAMP_TX_TO_RAC_CHANNEL; channel.num_of_params = 1; channel.param_num[0] = COM_TIMESTAMP_TX_TO_RAC_PARAM; channel.channel_handle = h_edma_handle; channel.param_handle = &h_edma_param[0]; com_edma3_channel_init(&channel); param_setup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_DIS, /*Intermediate chaining Enabled*/ CSL_EDMA3_TCCH_DIS,/*Final chaining Enabled*/ CSL_EDMA3_ITCINT_DIS,/*Intermediate Interrupt Disabled*/ CSL_EDMA3_TCINT_DIS, /*Final Interrupt Disabled*/ COM_INVALID_EDMA_CHANNEL,/*No need to Chain To ANY channel*/ CSL_EDMA3_TCC_NORMAL,/* TCC Mode is normal*/ CSL_EDMA3_FIFOWIDTH_NONE, /* FIFO is disabled*/ CSL_EDMA3_STATIC_EN, /* Static option disabled*/ CSL_EDMA3_SYNC_A, /* A-Synchronized Transfer*/ CSL_EDMA3_ADDRMODE_INCR, /* Source in increment mode*/ CSL_EDMA3_ADDRMODE_INCR /* Destination in increment mode*/ ); // param_setup.srcAddr = (u32_t)(&input_src_buff[0] | 0x10000000 );//(u32_t)(gbl_handle_fsync->regs->SYSVAL); /** Source address : SYSTEM Time Register of FSYNC */ param_setup.srcAddr = (u32_t)&(gbl_handle_fsync->regs->SYSVAL); /** Source address : SYSTEM Time Register of FSYNC */ param_setup.aCntbCnt = CSL_EDMA3_CNT_MAKE(sizeof(u32_t),1); /** One U32 value "SYSVAL" */ // param_setup.dstAddr = (u32_t)(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_ANT[0]);//(u32_t)(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_TIME); /** Destination address : Front End Time Register of RAC */ param_setup.dstAddr = (u32_t)&(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_TIME); /** Destination address : Front End Time Register of RAC */ param_setup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(sizeof(CSL_Edma3ParamSetup),0); param_setup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(COM_EDMA_PARAM_OFFSET(EDMA_SRIO_LINK_NULL),0); param_setup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0); param_setup.cCnt = 1; com_edma3_param_setup(&h_edma_param[0], ¶m_setup); /**2nd Channel: Channel #13 and PaRAM #: This Channel does Data Transfer from AIF to RAC FEI every 8 chips (For all 54 streams data. This is for entier AIF as such and not one a per link basis). This Channel is triggered by FSYNC event FSEVT3. This is connected to CIC input #5. This is routed to CIC output #5, which is conectd to EDMA channel #11 */ link_index = 0; channel.param_num = ¶m_num[0]; channel.param_handle = ¶m_handle; channel.channel_obj_ptr = &h_edma_obj; channel.edma_channel_num = COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_CHANNEL; channel.num_of_params = 4; channel.param_num[0] = COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_0; channel.param_num[1] = COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_1; channel.param_num[2] = COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_2; channel.param_num[3] = COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_3; channel.channel_handle = h_edma_handle; channel.param_handle = &h_edma_param[0]; com_edma3_channel_init(&channel); param_setup.option = CSL_EDMA3_OPT_MAKE( CSL_EDMA3_ITCCH_EN, /*Intermediate chaining Enabled*/ CSL_EDMA3_TCCH_EN,/*Final chaining Enabled*/ CSL_EDMA3_ITCINT_DIS,/*Intermediate Interrupt Disabled*/ CSL_EDMA3_TCINT_DIS, /*Final Interrupt Disabled*/ COM_INVALID_EDMA_CHANNEL/*COM_DEBUG_VALUE_CHANNEL/*0xFFFF*/,/*Chain To ANY channel??????*/ CSL_EDMA3_TCC_NORMAL,/* TCC Mode is normal*/ CSL_EDMA3_FIFOWIDTH_NONE, /* FIFO is disabled*/ CSL_EDMA3_STATIC_DIS, /* Static option disabled*/ CSL_EDMA3_SYNC_A, /* A-Synchronized Transfer*/ CSL_EDMA3_ADDRMODE_INCR, /* Source in increment mode*/ CSL_EDMA3_ADDRMODE_INCR /* Destination in increment mode*/ ); /** This should be able to transfer data after each 8-chip event from FSYNC (so 4 times in a 32chip RAC iteration period)*/ // param_setup.aCntbCnt = // CSL_EDMA3_CNT_MAKE(sizeof(CSL_Edma3ParamSetup), // HWIF_SRIO_NUM_LSU_REG_SETS * HWIF_NUM_L2_PARAMS_PER_PACKET_TRANSFER); param_setup.aCntbCnt = CSL_EDMA3_CNT_MAKE(sizeof (input1_src_buff),1); param_setup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(sizeof(CSL_Edma3ParamSetup),0); param_setup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0); param_setup.cCnt = 1; /** \todo PLEASE UPDATE SRC(AIF) AND DESTINATION (RAC) FOR THIS EDMA CONFIGURATION*/ /** Param-0 - To transfer 0-7 chips' data from AIF to RAC*/ link_index = 0; chipint8_cnt = 0; param_setup.linkBcntrld = /*CSL_EDMA3_LINKBCNTRLD_MAKE(COM_EDMA_PARAM_OFFSET(EDMA_SRIO_LINK_NULL),0);*/ CSL_EDMA3_LINKBCNTRLD_MAKE(COM_EDMA_PARAM_OFFSET(COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_1),0); /** Check this Address*/ // param_setup.srcAddr =(u32_t)(CSL_AIF_0_DATA + (link_index*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES*4) // + chipint8_cnt*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES); // param_setup.srcAddr = ((u32_t)&input1_src_buff[0] | 0x10000000); param_setup.dstAddr = (u32_t)&(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_ANT[RAC_FEI_BUFFER_0_INDEX]); /** RAC FIFO for (interrupt_index*) */ com_edma3_param_setup(&h_edma_param[chipint8_cnt], ¶m_setup); //#if 0 /** Param-1 - To transfer 8-15 chips' data from AIF to RAC*/ link_index = 0; chipint8_cnt = 1; param_setup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(COM_EDMA_PARAM_OFFSET(COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_2),0); /** Check this Address*/ // param_setup.srcAddr =(u32_t)(CSL_AIF_0_DATA + (link_index*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES*4) // + chipint8_cnt*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES); param_setup.srcAddr = ((u32_t)&input2_src_buff[0] | 0x10000000); param_setup.dstAddr = (u32_t)&(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_ANT[RAC_FEI_BUFFER_1_INDEX]); /** RAC FIFO for (interrupt_index*) */ com_edma3_param_setup(&h_edma_param[chipint8_cnt], ¶m_setup); /** Param-2 - To transfer 16-23 chips' data from AIF to RAC*/ link_index = 0; chipint8_cnt = 2; param_setup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(COM_EDMA_PARAM_OFFSET(COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_3),0); /** Check this Address*/ // param_setup.srcAddr =(u32_t)(CSL_AIF_0_DATA + (link_index*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES*4) // + chipint8_cnt*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES); param_setup.srcAddr = ((u32_t)&input3_src_buff[0] | 0x10000000); param_setup.dstAddr = (u32_t)&(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_ANT[RAC_FEI_BUFFER_2_INDEX]); /** RAC FIFO for (interrupt_index*) */ com_edma3_param_setup(&h_edma_param[chipint8_cnt], ¶m_setup); /** Param-3 - To transfer 24-31 chips' data from AIF to RAC*/ link_index = 0; chipint8_cnt = 3; param_setup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(COM_EDMA_PARAM_OFFSET(COM_8CHIP_TRIGGER_AIF_TO_RAC_UL_PARAM_0),0); /** Check this Address*/ // param_setup.srcAddr =(u32_t)(CSL_AIF_0_DATA + (link_index*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES*4) // + chipint8_cnt*EXEC_AIF_DATA_BLOCK_SIZE_IN_BYTES); param_setup.srcAddr = ((u32_t)&rac_debug_src_value/*input4_src_buff[0]*/ | 0x10000000); param_setup.dstAddr = /*((u32_t)&rac_debug_dest_value/*input4_src_buff[0] | 0x10000000);*/ (u32_t)&(((CSL_Rac_dataRegs*)CSL_RAC_DATA)->FE_ANT[RAC_FEI_BUFFER_3_INDEX]); /** RAC FIFO for (interrupt_index*) */ com_edma3_param_setup(&h_edma_param[chipint8_cnt], ¶m_setup); //#endif /** \NOTE EDMA3 Channel Configuration is not needed for AIF frame synchronization tick (10 ms). FSYNC can directly generate event to AIF and nothing else needs to happen through EDMA*/ } /** 2 AIF links are connected between FPGA-A and DSP. Hence configure only these two links. Shoould these be in 2x mode?????*/ void exec_aif_init_config() { /**HW provision: two (2) AIF SERDES links connected to FPGA-A. Hence it can operate in 2x mode.*/ CSL_aifInit(); } void exec_fsync_cpc_init() { /** Reset the FSYNC Control Register 2 which will HALT the timer and resets the 'RUN' bit*/ reg_ptr=(u32_t *)FSYNC_CTRL_REG2_ADDR; *reg_ptr=FSYNC_CTRL_REG2_RESETVAL; /** Initialize CSL library, this step is required */ CSL_fsyncInit(NULL); /** Clear the input structures*/ memset(&fsync_cfg,0,sizeof(CSL_FsyncSetup)); memset(&config_mask_trigger,0,sizeof(CSL_FsyncMaskTriggerGenObj)); memset(&fsync_err_event_mask_cfg,0,sizeof(CSL_FsyncMaskTriggerGenObj)); /** Open handle for link 0 - for use */ gbl_handle_fsync = CSL_fsyncOpen(&gbl_obj_fsync, CSL_FSYNC, NULL,&status); if ((gbl_handle_fsync == NULL) || (status != CSL_SOK)) { EXEC_PRINT("FSYNC handle cannot be opened , error number %d.\n",CSL_API_FAILURE_ERRNO); SYS_error(CSL_API_FAILURE_ERRSTR, CSL_API_FAILURE_ERRNO, __FILE__, __LINE__); } /** Fsync CONFIGURATIONS*/ sys_terminal_count.lastSlotNum = SLOTS_PER_FRAME -1; /** 1x clock. This field gives number of valid entries in SYSTC_RAM. By setting it to "0", we are fixing only one terminal count is used for CHIP count*/ sys_terminal_count.lastSampleNum = FSYNC_SAMPLES_PER_CHIP -1; sys_terminal_count.numChipTerminalCount = 1; for(loop_counter=0;loop_counter 10 ms trigger to AIF CSL_FSYNC_TRIGGER_GEN_5 -> 8 Chips tick for AIF to RAC data transfer CSL_FSYNC_TRIGGER_GEN_10 -> 32 Chip Trigger to copy timestamp from FSYNC to RAC CSL_FSYNC_TRIGGER_GEN_4 -> 32 Chip Trigger to Start RAC Iteration procesing **************************************************************************** */ /** Configure RP3 timer for generating UMTS frame sync All Mask bits are enabled to count until terminal count value (Triggers event once per 10 ms) */ config_rp3_mask_trigger[0].timerUsed = CSL_FSYNC_RP3_TIMER; config_rp3_mask_trigger[0].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_1; /* to AIF*/ config_rp3_mask_trigger[0].mask.frameMask = 0x0; config_rp3_mask_trigger[0].mask.slotMask = 0xFF; config_rp3_mask_trigger[0].mask.chipTerminalCountIndexMask = 0x0; config_rp3_mask_trigger[0].mask.chipMask = 0xFFFF; config_rp3_mask_trigger[0].mask.sampleMask = 0xFF; config_rp3_mask_trigger[0].offset.slotOffset = 0; config_rp3_mask_trigger[0].offset.chipTerminalCountIndex = 0x0; config_rp3_mask_trigger[0].offset.chipOffset = 0; config_rp3_mask_trigger[0].offset.sampleOffset = 0; config_rp3_mask_trigger[0].compareValue.slotValue = 0; config_rp3_mask_trigger[0].compareValue.chipTerminalCountIndexValue = 0x0; config_rp3_mask_trigger[0].compareValue.chipValue = 0; config_rp3_mask_trigger[0].compareValue.sampleValue = 0; /** Configure RP3 timer for generating UMTS frame sync (8 chips tick for EDMA inbound data transfer from AIF-RAM to RAC-FIFO ) */ config_rp3_mask_trigger[1].timerUsed = CSL_FSYNC_RP3_TIMER; config_rp3_mask_trigger[1].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_5; config_rp3_mask_trigger[1].mask.frameMask = 0x0; config_rp3_mask_trigger[1].mask.slotMask = 0x0; config_rp3_mask_trigger[1].mask.chipTerminalCountIndexMask = 0x0; config_rp3_mask_trigger[1].mask.chipMask = 0x7; config_rp3_mask_trigger[1].mask.sampleMask = 0xFF; /** lag of 8 chips between AIF write and EDMA read */ config_rp3_mask_trigger[1].offset.slotOffset = 0x1; config_rp3_mask_trigger[1].offset.chipTerminalCountIndex = 0x0; config_rp3_mask_trigger[1].offset.chipOffset = 0x1; config_rp3_mask_trigger[1].offset.sampleOffset = 0x0; config_rp3_mask_trigger[1].compareValue.slotValue = 0x0; /** don\’t care since there is only 1 terminal count in WCDMA */ config_rp3_mask_trigger[1].compareValue.chipTerminalCountIndexValue = 0x0; config_rp3_mask_trigger[1].compareValue.chipValue = 0x1; config_rp3_mask_trigger[1].compareValue.sampleValue = 0x0; /** Event to trigger ticks every 32-chips, to copy Timestamp from FSYNC to RAC, for next cycle of processing */ config_rp3_counter_trigger[1].timerUsed = CSL_FSYNC_RP3_TIMER; config_rp3_counter_trigger[1].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_10; config_rp3_counter_trigger[1].eventCount = 4*(/*SAMPLE_COUNT_WRAP_WCDMA_FDD+*/1)-1; config_rp3_counter_trigger[1].offset.slotOffset = 0; config_rp3_counter_trigger[1].offset.chipTerminalCountIndex = 0; config_rp3_counter_trigger[1].offset.chipOffset = 12; config_rp3_counter_trigger[1].offset.sampleOffset = 0; /** 32 chips Event Trigger to Start RAC Processing */ config_rp3_counter_trigger[2].timerUsed = CSL_FSYNC_RP3_TIMER; config_rp3_counter_trigger[2].eventGenUsed = CSL_FSYNC_TRIGGER_GEN_4; config_rp3_counter_trigger[2].eventCount = 4*(/*SAMPLE_COUNT_WRAP_WCDMA_FDD+*/1)-1; config_rp3_counter_trigger[2].offset.slotOffset = 0; config_rp3_counter_trigger[2].offset.chipTerminalCountIndex = 0; config_rp3_counter_trigger[2].offset.chipOffset = 12; config_rp3_counter_trigger[2].offset.sampleOffset = 0; /** Related to FSYNC Error status reporting*/ /** Program Err Set Mask 0 to enable System Frame Error condition*/ /** To report Error from FSYNC.This will trigger CPUINT 10*/ fsync_err_event_mask_cfg.errEventMask0 = CSL_FSYNC_SYSTEM_FRAME_FAIL; fsync_err_event_mask_cfg.errEventMask1 = 0; CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_ERR_EVENT, (void *)&fsync_err_event_mask_cfg); /** Initialize the symbol interrupt counter*/ hwi_symbol_int_cnt=0; /** Configure mask based trigger generator 1 for System Timer*/ CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&config_mask_trigger); /** Enable trigger generator 1 for System Timer*/ CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(config_mask_trigger.eventGenUsed)); /** Configure mask based trigger generator 1 for RP3 timer*/ /** Enable trigger generator 1 for RP3 timer*/ CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&config_rp3_mask_trigger[0]); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(config_rp3_mask_trigger[0].eventGenUsed)); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_CONFIG_MASK_BASED_TRIGGER_GEN, (void *)&config_rp3_mask_trigger[1]); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(config_rp3_mask_trigger[1].eventGenUsed)); /** Enable counter Based timer*/ CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_CONFIG_COUNTER_BASED_TRIGGER_GEN, (void *)&config_rp3_counter_trigger[0]); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(config_rp3_counter_trigger[0].eventGenUsed)); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_CONFIG_COUNTER_BASED_TRIGGER_GEN, (void *)&config_rp3_counter_trigger[1]); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(config_rp3_counter_trigger[1].eventGenUsed)); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_CONFIG_COUNTER_BASED_TRIGGER_GEN, (void *)&config_rp3_counter_trigger[2]); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TRIGGER_GEN, (void *)&(config_rp3_counter_trigger[2].eventGenUsed)); /** Enable System Timer*/ fsync_ctrl_arg = CSL_FSYNC_SYSTEM_TIMER_ENABLE; CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TIMER, (void *)&fsync_ctrl_arg); /** Enable RP3 Timer*/ fsync_ctrl_arg = CSL_FSYNC_RP3_TIMER_ENABLE; CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_ENABLE_TIMER, (void *)&fsync_ctrl_arg); /** Start FSYNC by setting Frame-Sync run bit*/ CSL_fsyncSetOkStatBit(gbl_handle_fsync); CSL_fsyncHwControl(gbl_handle_fsync, CSL_FSYNC_CMD_TRIGGER_SYSTEM_TEST_SYNC, NULL); }