/*<COPYRIGHT>*/
/******************************************************************************
*                                                                             *
*   CUMMINS INC.                                                              *
*   COPYRIGHT 2011 CUMMINS INC.  ALL RIGHTS RESERVED                          *
*   This program may not be reproduced, in whole or in part in any form       *
*   or by any means whatsoever without the written permission of:             *
*       CUMMINS INC.                                                          *
*       P.O. Box 3005                                                         *
*       Columbus, IN 47202-3005                                               *
*                                                                             *
*   Revision History: Please use ClearCase to get the revision history.       *
*                                                                             *
******************************************************************************/
/*</COPYRIGHT>*/

MEMORY
{
   /* Program Memory */
   PAGE 0: INTERNAL_FLASH:         origin=0x300000            length=0x03FF80
   PAGE 0: RESET:                  origin=0x33FFF6            length=0x000002
   PAGE 0: PWL:                    origin=0x33FFF8            length=0x000008   fill=0xFFFF

   /* Data Memory */
   PAGE 1: STACK:                  origin=0x000000            length=0x000800	
   PAGE 1: INTERNAL_RAM:           origin=0x008000            length=0x008000
   
   /* Peripheral Registers */ 
   PAGE 2: ADC_REGS:                origin=0x007100           length=0x000020
   PAGE 2: ADC_MIRROR_REGS:         origin=0x000B00           length=0x000010
   PAGE 2: CPU_TIMER0_REGS:         origin=0x000C00           length=0x000008
   PAGE 2: CPU_TIMER1_REGS:         origin=0x000C08           length=0x000008
   PAGE 2: CPU_TIMER2_REGS:         origin=0x000C10           length=0x000008     
   PAGE 2: CSMPWL_REGS:             origin=0x33FFF8           length=0x000008
   PAGE 2: CSM_REGS:                origin=0x000AE0           length=0x000010
   PAGE 2: DEV_EMU_REGS:            origin=0x000880           length=0x000180
   PAGE 2: DMA_REGS:				origin=0x001000           length=0x000200
   PAGE 2: ECANALAM_REGS:           origin=0x006040           length=0x000040
   PAGE 2: ECANAMOTO_REGS:          origin=0x0060C0           length=0x000040
   PAGE 2: ECANAMOTS_REGS:          origin=0x006080           length=0x000040
   PAGE 2: ECANAMBOX_REGS:          origin=0x006100           length=0x000100   
   PAGE 2: ECANA_REGS:              origin=0x006000           length=0x000040   
   PAGE 2: ECANBLAM_REGS:           origin=0x006240           length=0x000040
   PAGE 2: ECANBMOTO_REGS:          origin=0x0062C0           length=0x000040
   PAGE 2: ECANBMOTS_REGS:          origin=0x006280           length=0x000040
   PAGE 2: ECANBMBOX_REGS:          origin=0x006300           length=0x000100   
   PAGE 2: ECANB_REGS:              origin=0x006200           length=0x000040          
   PAGE 2: ECAP1_REGS:              origin=0x006A00           length=0x000020
   PAGE 2: ECAP2_REGS:              origin=0x006A20           length=0x000020
   PAGE 2: ECAP3_REGS:              origin=0x006A40           length=0x000020
   PAGE 2: ECAP4_REGS:              origin=0x006A60           length=0x000020         
   PAGE 2: ECAP5_REGS:              origin=0x006A80           length=0x000020
   PAGE 2: ECAP6_REGS:              origin=0x006AA0           length=0x000020   
   PAGE 2: EPWM1_REGS:              origin=0x006800           length=0x000022   
   PAGE 2: EPWM2_REGS:              origin=0x006840           length=0x000022
   PAGE 2: EPWM3_REGS:              origin=0x006880           length=0x000022
   PAGE 2: EPWM4_REGS:              origin=0x0068C0           length=0x000022
   PAGE 2: EPWM5_REGS:              origin=0x006900           length=0x000022
   PAGE 2: EPWM6_REGS:              origin=0x006940           length=0x000022 
   PAGE 2: PARTID_REGS:				origin=0x380090           length=0x000001 
   PAGE 2: EQEP1_REGS:              origin=0x006B00           length=0x000040       
   PAGE 2: EQEP2_REGS:              origin=0x006B40           length=0x000040
   PAGE 2: FLASH_REGS:              origin=0x000A80           length=0x000060
   PAGE 2: GPIOCTRL_REGS:           origin=0x006F80           length=0x000040
   PAGE 2: GPIODATA_REGS:			origin=0x006FC0           length=0x000020
   PAGE 2: GPIOINT_REGS:			origin=0x006FE0           length=0x000020
   PAGE 2: I2CA_REGS:               origin=0x007900           length=0x000040
   PAGE 2: MCBSPA_REGS:				origin=0x005000           length=0x000040
   PAGE 2: MCBSPB_REGS:				origin=0x005040           length=0x000040   
   PAGE 2: PIECTRL_REGS:			origin=0x000CE0           length=0x000020
   PAGE 2: PIEVECT_REGS:            origin=0x000D00           length=0x000100
   PAGE 2: SCIA_REGS:               origin=0x007050           length=0x000010
   PAGE 2: SCIB_REGS:               origin=0x007750           length=0x000010
   PAGE 2: SCIC_REGS:               origin=0x007770           length=0x000010    
   PAGE 2: SPIA_REGS:               origin=0x007040           length=0x000010
   PAGE 2: SYSCTRL_REGS:            origin=0x007010           length=0x000020  
   PAGE 2: XINTERRUPT_REGS:         origin=0x007070           length=0x000010
   PAGE 2: XINT_REGS:               origin=0x000B20           length=0x000020
            
}

SECTIONS
{	
   .stack:     {*(.stack)} > STACK PAGE = 1 START(_STACK_START_MARKER) END(_STACK_END_MARKER)
   .ebss:      {*(.ebss)} > INTERNAL_RAM PAGE = 1
   
   .codeinram: LOAD = INTERNAL_FLASH PAGE = 0, RUN = INTERNAL_RAM PAGE = 1
               {
                  . = ALIGN(4);
                  *(.codeinram)   
                  . = ALIGN(4);              
               } RUN_START(__R_CODE_IN_RAM_START) LOAD_START(__F_CODE_IN_RAM_START) LOAD_END(__F_CODE_IN_RAM_END)

   GROUP :
   {
      .econst:  {*(.econst)}
      .text:    {*(.text)}
      .cinit:   {*(.cinit)}
	  .switch:  {*(.switch)}
   
   } > INTERNAL_FLASH PAGE = 0
        
   .dmyvarinit
   {
     _INTERNAL_RAM_START = 0x8000;
     _INTERNAL_RAM_SIZE  = 0x8000;
     _application_internal_ram_start = 0x0;
     _application_internal_ram_end   = 0x0;
     _devcal_init_data_start         = 0x0;
     _devcal_init_data_end           = 0x0;
     _devcal_ram_copy_start          = 0x0;
     _devextcal_init_data_start      = 0x0;
     _devextcal_init_data_end        = 0x0;
     _devextcal_ram_copy_start       = 0x0;     
     _downloaded_eeprom_end          = 0x0;
     _eeprom_ram_image_start         = 0x0;
     _eeprom_start                   = 0x0;
     _esm_check_powerdown_errors_init = 0x0;
     
     _PWDN_Application_Ram_Start     = 0x0;
     _PWDN_Application_Ram_End       = 0x0;  
     _PWDN_FixedNDL_Flash_End        = 0x0;
     _PWDN_Ram_Copy_Start            = 0x0;   
     
     _SOR_Application_Ram_Start     = 0x0;
     _SOR_Application_Ram_End       = 0x0;  
     _SOR_FixedNDL_Flash_End        = 0x0;
     _SOR_FixedDL_Ram_End           = 0x0;     
     _SOR_Ram_Copy_Start            = 0x0;  
     _Trims_Ram_Copy_End            = 0x0;
     _external_ram_end              = 0x0;
     
     _esm_check_powerdown_errors    = 0x0;
     _esm_savepowerdowndata         = 0x0;
     _esm_savesordata               = 0x0;
     _esm_savepowerdowndata_init    = 0x0;     
     _esm_oscillator_monitor_error_init = 0x0;
     _esm_oscillator_monitor_error  = 0x0;
     
     _protected_ram_start           = 0x0;
     _Flash_Block_Total_End         = 0x0;
     _Flash_Block_Total_Start	    = 0x0;
     _SOR_Block_Checksum			= 0x0;
     _SOR_Block_Count_Copy_1		= 0x0;
     _SOR_Block_Count_Copy_2		= 0x0;
     _PDB_Block_Checksum			= 0x0;
     _PDB_Block_Count_Copy_1		= 0x0; 
     _PDB_Block_Count_Copy_2		= 0x0; 
     
     _checksum_table_block0_start	= 0x0;    
     _checksum_table_block0_end		= 0x0; 
     _checksum_table_block1_start	= 0x0;    
     _checksum_table_block1_end		= 0x0;      
   }
   
   .reset  {*(.reset)} > RESET PAGE = 0
   
   .adcregs:        {*(AdcRegsFile)}       > ADC_REGS        PAGE = 2
   .adcmirrorregs:  {*(AdcMirrorFile)}     > ADC_MIRROR_REGS PAGE = 2   
   .cputimer0regs:  {*(CpuTimer0RegsFile)} > CPU_TIMER0_REGS PAGE = 2
   .cputimer1regs:  {*(CpuTimer1RegsFile)} > CPU_TIMER1_REGS PAGE = 2
   .cputimer2regs:  {*(CpuTimer2RegsFile)} > CPU_TIMER2_REGS PAGE = 2 
   .csmpwlregs:     {*(CsmPwlFile)}        > CSMPWL_REGS     PAGE = 2
   .csmregs:        {*(CsmRegsFile)}       > CSM_REGS        PAGE = 2
   .devemuregs:     {*(DevEmuRegsFile)}    > DEV_EMU_REGS    PAGE = 2   
   .dmaregs:        {*(DmaRegsFile)}       > DMA_REGS        PAGE = 2
   .ecanalamregs:   {*(ECanaLAMRegsFile)}  > ECANALAM_REGS   PAGE = 2
   .ecanamotoregs:  {*(ECanaMOTORegsFile)} > ECANAMOTO_REGS  PAGE = 2
   .ecanamotsregs:  {*(ECanaMOTSRegsFile)} > ECANAMOTS_REGS  PAGE = 2
   .ecanamboxregs:  {*(ECanaMboxesFile)}   > ECANAMBOX_REGS  PAGE = 2   
   .ecanaregs:      {*(ECanaRegsFile)}     > ECANA_REGS      PAGE = 2                    
   .ecanblamregs:   {*(ECanbLAMRegsFile)}  > ECANBLAM_REGS   PAGE = 2
   .ecanbmotoregs:  {*(ECanbMOTORegsFile)} > ECANBMOTO_REGS  PAGE = 2
   .ecanbmotsregs:  {*(ECanbMOTSRegsFile)} > ECANBMOTS_REGS  PAGE = 2
   .ecanbmboxregs:  {*(ECanbMboxesFile)}   > ECANBMBOX_REGS  PAGE = 2   
   .ecanbregs:      {*(ECanbRegsFile)}     > ECANB_REGS      PAGE = 2  
   .ecap1regs:      {*(ECap1RegsFile)}     > ECAP1_REGS      PAGE = 2    
   .ecap2regs:      {*(ECap2RegsFile)}     > ECAP2_REGS      PAGE = 2    
   .ecap3regs:      {*(ECap3RegsFile)}     > ECAP3_REGS      PAGE = 2    
   .ecap4regs:      {*(ECap4RegsFile)}     > ECAP4_REGS      PAGE = 2 
   .ecap5regs:      {*(ECap5RegsFile)}     > ECAP5_REGS      PAGE = 2 
   .ecap6regs:      {*(ECap6RegsFile)}     > ECAP6_REGS      PAGE = 2     
   .epwm1regs:      {*(EPwm1RegsFile)}     > EPWM1_REGS		 PAGE = 2     
   .epwm2regs:      {*(EPwm2RegsFile)}     > EPWM2_REGS		 PAGE = 2
   .epwm3regs:      {*(EPwm3RegsFile)}     > EPWM3_REGS		 PAGE = 2
   .epwm4regs:      {*(EPwm4RegsFile)}     > EPWM4_REGS		 PAGE = 2
   .epwm5regs:      {*(EPwm5RegsFile)}     > EPWM5_REGS		 PAGE = 2
   .epwm6regs:      {*(EPwm6RegsFile)}     > EPWM6_REGS		 PAGE = 2 
   .partidregs:     {*(PartIdRegsFile)}    > PARTID_REGS     PAGE = 2   
   .eqep1regs:      {*(EQep1RegsFile)}     > EQEP1_REGS      PAGE = 2          
   .eqep2regs:      {*(EQep2RegsFile)}     > EQEP2_REGS      PAGE = 2 
   .flashres:       {*(FlashRegsFile)}     > FLASH_REGS      PAGE = 2
   .gpioctrlregs:   {*(GpioCtrlRegsFile)}  > GPIOCTRL_REGS   PAGE = 2  
   .gpiodataregs:   {*(GpioDataRegsFile)}  > GPIODATA_REGS   PAGE = 2 
   .gpiointregs:    {*(GpioIntRegsFile)}   > GPIOINT_REGS    PAGE = 2 
   .i2caregs:       {*(I2caRegsFile)}      > I2CA_REGS       PAGE = 2
   .mcbsparegs:     {*(McbspaRegsFile)}    > MCBSPA_REGS     PAGE = 2      
   .mcbspbregs:     {*(McbspbRegsFile)}    > MCBSPB_REGS     PAGE = 2 
   .piectrlregs:    {*(PieCtrlRegsFile)}   > PIECTRL_REGS    PAGE = 2
   .pievectregs:    {*(PieVectTableFile)}  > PIEVECT_REGS    PAGE = 2 START(_R_VECTABLE_START) SIZE(_R_VECTABLE_SIZE)
   .sciaregs:       {*(SciaRegsFile)}      > SCIA_REGS       PAGE = 2
   .scibregs:       {*(ScibRegsFile)}      > SCIB_REGS       PAGE = 2
   .scicregs:       {*(ScicRegsFile)}      > SCIC_REGS       PAGE = 2      
   .spiaregs:       {*(SpiaRegsFile)}      > SPIA_REGS       PAGE = 2
   .sysctrlregs:    {*(SysCtrlRegsFile)}   > SYSCTRL_REGS    PAGE = 2 
   .xinterruptregs: {*(XIntruptRegsFile)}  > XINTERRUPT_REGS PAGE = 2
   .xintregs:       {*(XintfRegsFile)}     > XINT_REGS       PAGE = 2
   
}

