Thu Jul 20 15:24:30 2023 Start Record Command (req) Thu Jul 20 15:24:31 2023 Start Record command : Success Thu Jul 20 15:24:31 2023 Return status : 0 Thu Jul 20 15:25:51 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 15:25:51 2023 Record stop is done successfully Thu Jul 20 15:30:54 2023 Start Record Command (req) Thu Jul 20 15:30:55 2023 Start Record command : Success Thu Jul 20 15:30:55 2023 Return status : 0 Thu Jul 20 15:32:15 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 15:32:25 2023 Record stop failed Thu Jul 20 15:34:36 2023 Start Record Command (req) Thu Jul 20 15:34:36 2023 Start Record command : Success Thu Jul 20 15:34:36 2023 Return status : 0 Thu Jul 20 15:35:56 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 15:36:06 2023 Record stop failed Thu Jul 20 16:08:57 2023 Read DLL Verison Command (req) Thu Jul 20 16:08:57 2023 DLL Version : 1.0 Thu Jul 20 16:09:17 2023 FPGA Configuration Command (req) Thu Jul 20 16:09:18 2023 FPGA Configuration command : Success Thu Jul 20 16:09:18 2023 Return status : 0 Thu Jul 20 16:09:18 2023 Configure Record Command (req) Thu Jul 20 16:09:18 2023 Configure Record command : Success Thu Jul 20 16:09:18 2023 Return status : 0 Thu Jul 20 16:09:18 2023 Read FPGA version Command (req) Thu Jul 20 16:09:18 2023 FPGA Version : 2.9 [Record] Thu Jul 20 16:09:48 2023 Start Record Command (req) Thu Jul 20 16:09:49 2023 Start Record command : Success Thu Jul 20 16:09:49 2023 Return status : 0 Thu Jul 20 16:11:09 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 16:11:09 2023 Record stop is done successfully Thu Jul 20 16:18:30 2023 Read DLL Verison Command (req) Thu Jul 20 16:18:30 2023 DLL Version : 1.0 Thu Jul 20 16:18:35 2023 FPGA Configuration Command (req) Thu Jul 20 16:18:35 2023 FPGA Configuration command : Success Thu Jul 20 16:18:35 2023 Return status : 0 Thu Jul 20 16:18:35 2023 Configure Record Command (req) Thu Jul 20 16:18:35 2023 Configure Record command : Success Thu Jul 20 16:18:35 2023 Return status : 0 Thu Jul 20 16:18:35 2023 Read FPGA version Command (req) Thu Jul 20 16:18:35 2023 FPGA Version : 2.9 [Record] Thu Jul 20 16:18:40 2023 Reset FPGA Command (req) Thu Jul 20 16:18:40 2023 Reset FPGA command : Success Thu Jul 20 16:18:40 2023 Return status : 0 Thu Jul 20 16:18:40 2023 FPGA Configuration Command (req) Thu Jul 20 16:18:40 2023 FPGA Configuration command : Success Thu Jul 20 16:18:40 2023 Return status : 0 Thu Jul 20 16:18:40 2023 Configure Record Command (req) Thu Jul 20 16:18:40 2023 Configure Record command : Success Thu Jul 20 16:18:40 2023 Return status : 0 Thu Jul 20 16:18:40 2023 Read FPGA version Command (req) Thu Jul 20 16:18:40 2023 FPGA Version : 2.9 [Record] Thu Jul 20 16:18:49 2023 Reset FPGA Command (req) Thu Jul 20 16:18:49 2023 Reset FPGA command : Success Thu Jul 20 16:18:49 2023 Return status : 0 Thu Jul 20 16:18:49 2023 FPGA Configuration Command (req) Thu Jul 20 16:18:49 2023 FPGA Configuration command : Success Thu Jul 20 16:18:49 2023 Return status : 0 Thu Jul 20 16:18:49 2023 Configure Record Command (req) Thu Jul 20 16:18:49 2023 Configure Record command : Success Thu Jul 20 16:18:49 2023 Return status : 0 Thu Jul 20 16:18:50 2023 Read FPGA version Command (req) Thu Jul 20 16:18:50 2023 FPGA Version : 2.9 [Record] Thu Jul 20 16:19:13 2023 Start Record Command (req) Thu Jul 20 16:19:13 2023 Start Record command : Success Thu Jul 20 16:19:13 2023 Return status : 0 Thu Jul 20 16:20:33 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 16:20:34 2023 Record stop is done successfully Thu Jul 20 16:24:57 2023 Start Record Command (req) Thu Jul 20 16:24:57 2023 Start Record command : Success Thu Jul 20 16:24:57 2023 Return status : 0 Thu Jul 20 16:26:17 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 16:26:27 2023 Record stop failed Thu Jul 20 16:34:09 2023 Start Record Command (req) Thu Jul 20 16:34:09 2023 Start Record command : Success Thu Jul 20 16:34:09 2023 Return status : 0 Thu Jul 20 16:34:38 2023 No LVDS data Thu Jul 20 16:34:38 2023 No Header Thu Jul 20 16:34:38 2023 Record stop is done successfully Thu Jul 20 16:35:29 2023 Read DLL Verison Command (req) Thu Jul 20 16:35:29 2023 DLL Version : 1.0 Thu Jul 20 16:35:31 2023 FPGA Configuration Command (req) Thu Jul 20 16:35:31 2023 FPGA Configuration command : Success Thu Jul 20 16:35:31 2023 Return status : 0 Thu Jul 20 16:35:31 2023 Configure Record Command (req) Thu Jul 20 16:35:31 2023 Configure Record command : Success Thu Jul 20 16:35:31 2023 Return status : 0 Thu Jul 20 16:35:31 2023 Read FPGA version Command (req) Thu Jul 20 16:35:31 2023 FPGA Version : 2.9 [Record] Thu Jul 20 16:35:43 2023 Reset FPGA Command (req) Thu Jul 20 16:35:43 2023 Reset FPGA command : Success Thu Jul 20 16:35:43 2023 Return status : 0 Thu Jul 20 16:35:43 2023 FPGA Configuration Command (req) Thu Jul 20 16:35:43 2023 FPGA Configuration command : Success Thu Jul 20 16:35:43 2023 Return status : 0 Thu Jul 20 16:35:43 2023 Configure Record Command (req) Thu Jul 20 16:35:43 2023 Configure Record command : Success Thu Jul 20 16:35:43 2023 Return status : 0 Thu Jul 20 16:35:43 2023 Read FPGA version Command (req) Thu Jul 20 16:35:43 2023 FPGA Version : 2.9 [Record] Thu Jul 20 16:35:53 2023 Start Record Command (req) Thu Jul 20 16:35:53 2023 Start Record command : Success Thu Jul 20 16:35:53 2023 Return status : 0 Thu Jul 20 16:37:13 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 16:37:23 2023 Record stop failed Thu Jul 20 16:51:15 2023 Start Record Command (req) Thu Jul 20 16:51:15 2023 Start Record command : Success Thu Jul 20 16:51:15 2023 Return status : 0 Thu Jul 20 16:52:35 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 16:52:35 2023 Record stop is done successfully Thu Jul 20 16:52:54 2023 Start Record Command (req) Thu Jul 20 16:52:54 2023 Start Record command : Success Thu Jul 20 16:52:54 2023 Return status : 0 Thu Jul 20 16:54:14 2023 Record Process : Timeout Error! System disconnected Thu Jul 20 16:54:14 2023 Record stop is done successfully Thu Jul 20 16:54:40 2023 Read DLL Verison Command (req) Thu Jul 20 16:54:40 2023 DLL Version : 1.0 Thu Jul 20 16:54:44 2023 FPGA Configuration Command (req) Thu Jul 20 16:54:44 2023 FPGA Configuration command : Success Thu Jul 20 16:54:44 2023 Return status : 0 Thu Jul 20 16:54:44 2023 Configure Record Command (req) Thu Jul 20 16:54:44 2023 Configure Record command : Success Thu Jul 20 16:54:44 2023 Return status : 0 Thu Jul 20 16:54:44 2023 Read FPGA version Command (req) Thu Jul 20 16:54:44 2023 FPGA Version : 2.9 [Record] Thu Jul 20 16:54:53 2023 Start Record Command (req) Thu Jul 20 16:54:53 2023 Start Record command : Success Thu Jul 20 16:54:53 2023 Return status : 0 Thu Jul 20 16:55:00 2023 Record is completed Thu Jul 20 16:55:00 2023 Record stop is done successfully Thu Jul 20 16:55:33 2023 Start Record Command (req) Thu Jul 20 16:55:34 2023 Start Record command : Success Thu Jul 20 16:55:34 2023 Return status : 0 Thu Jul 20 16:55:40 2023 Record is completed Thu Jul 20 16:55:40 2023 Record stop is done successfully Tue Aug 01 15:30:45 2023 Start Record Command (req) Tue Aug 01 15:30:45 2023 Start Record command : Success Tue Aug 01 15:30:45 2023 Return status : 0 Tue Aug 01 15:32:05 2023 Record Process : Timeout Error! System disconnected Tue Aug 01 15:32:05 2023 Record stop is done successfully Tue Aug 01 15:41:39 2023 Read DLL Verison Command (req) Tue Aug 01 15:41:39 2023 DLL Version : 1.0 Tue Aug 01 15:41:45 2023 FPGA Configuration Command (req) Tue Aug 01 15:41:45 2023 FPGA Configuration command : Success Tue Aug 01 15:41:45 2023 Return status : 0 Tue Aug 01 15:41:45 2023 Configure Record Command (req) Tue Aug 01 15:41:45 2023 Configure Record command : Success Tue Aug 01 15:41:45 2023 Return status : 0 Tue Aug 01 15:41:45 2023 Read FPGA version Command (req) Tue Aug 01 15:41:45 2023 FPGA Version : 2.9 [Record] Tue Aug 01 15:45:28 2023 Start Record Command (req) Tue Aug 01 15:45:29 2023 Start Record command : Success Tue Aug 01 15:45:29 2023 Return status : 0 Tue Aug 01 15:45:42 2023 Record is completed Tue Aug 01 15:45:42 2023 Record stop is done successfully Tue Aug 01 16:13:13 2023 Start Record Command (req) Tue Aug 01 16:13:13 2023 Start Record command : Success Tue Aug 01 16:13:13 2023 Return status : 0 Tue Aug 01 16:13:19 2023 Record is completed Tue Aug 01 16:13:19 2023 Record stop is done successfully Tue Aug 01 16:19:29 2023 Start Record Command (req) Tue Aug 01 16:19:30 2023 Start Record command : Success Tue Aug 01 16:19:30 2023 Return status : 0 Tue Aug 01 16:19:34 2023 Record is completed Tue Aug 01 16:19:34 2023 Record stop is done successfully Tue Aug 01 16:20:27 2023 Start Record Command (req) Tue Aug 01 16:20:28 2023 Start Record command : Success Tue Aug 01 16:20:28 2023 Return status : 0 Tue Aug 01 16:20:33 2023 Record is completed Tue Aug 01 16:20:33 2023 Record stop is done successfully Tue Aug 01 16:27:29 2023 Start Record Command (req) Tue Aug 01 16:27:30 2023 Start Record command : Success Tue Aug 01 16:27:30 2023 Return status : 0 Tue Aug 01 16:27:41 2023 Record is completed Tue Aug 01 16:27:41 2023 Record stop is done successfully Tue Aug 01 16:30:02 2023 Start Record Command (req) Tue Aug 01 16:30:02 2023 Start Record command : Success Tue Aug 01 16:30:02 2023 Return status : 0 Tue Aug 01 16:30:09 2023 Record is completed Tue Aug 01 16:30:09 2023 Record stop is done successfully Tue Aug 01 16:36:25 2023 Start Record Command (req) Tue Aug 01 16:36:25 2023 Start Record command : Success Tue Aug 01 16:36:25 2023 Return status : 0 Tue Aug 01 16:36:31 2023 Record is completed Tue Aug 01 16:36:31 2023 Record stop is done successfully Tue Aug 01 16:41:37 2023 Start Record Command (req) Tue Aug 01 16:41:37 2023 Start Record command : Success Tue Aug 01 16:41:37 2023 Return status : 0 Tue Aug 01 16:41:42 2023 Record is completed Tue Aug 01 16:41:42 2023 Record stop is done successfully Tue Aug 01 16:43:14 2023 Start Record Command (req) Tue Aug 01 16:43:14 2023 Start Record command : Success Tue Aug 01 16:43:14 2023 Return status : 0 Tue Aug 01 16:43:19 2023 Record is completed Tue Aug 01 16:43:19 2023 Record stop is done successfully Tue Aug 01 17:08:58 2023 Read DLL Verison Command (req) Tue Aug 01 17:08:58 2023 DLL Version : 1.0 Tue Aug 01 17:09:01 2023 FPGA Configuration Command (req) Tue Aug 01 17:09:01 2023 FPGA Configuration command : Success Tue Aug 01 17:09:01 2023 Return status : 0 Tue Aug 01 17:09:01 2023 Configure Record Command (req) Tue Aug 01 17:09:01 2023 Configure Record command : Success Tue Aug 01 17:09:01 2023 Return status : 0 Tue Aug 01 17:09:01 2023 Read FPGA version Command (req) Tue Aug 01 17:09:01 2023 FPGA Version : 2.9 [Record] Tue Aug 01 17:09:47 2023 Start Record Command (req) Tue Aug 01 17:09:47 2023 Start Record command : Success Tue Aug 01 17:09:47 2023 Return status : 0 Tue Aug 01 17:09:54 2023 Record is completed Tue Aug 01 17:09:54 2023 Record stop is done successfully Tue Aug 01 18:24:28 2023 Start Record Command (req) Tue Aug 01 18:24:28 2023 Start Record command : Success Tue Aug 01 18:24:28 2023 Return status : 0 Tue Aug 01 18:25:48 2023 Record Process : Timeout Error! System disconnected Tue Aug 01 18:25:48 2023 Record stop is done successfully Tue Aug 01 18:27:01 2023 FPGA Configuration Command (req) Tue Aug 01 18:27:01 2023 FPGA Configuration command : Success Tue Aug 01 18:27:01 2023 Return status : 0 Tue Aug 01 18:27:01 2023 Configure Record Command (req) Tue Aug 01 18:27:01 2023 Configure Record command : Success Tue Aug 01 18:27:01 2023 Return status : 0 Tue Aug 01 18:27:01 2023 Read FPGA version Command (req) Tue Aug 01 18:27:01 2023 FPGA Version : 2.9 [Record] Tue Aug 01 18:27:35 2023 Start Record Command (req) Tue Aug 01 18:27:35 2023 Start Record command : Success Tue Aug 01 18:27:35 2023 Return status : 0 Tue Aug 01 18:27:40 2023 Record is completed Tue Aug 01 18:27:40 2023 Record stop is done successfully Tue Aug 01 19:25:57 2023 Start Record Command (req) Tue Aug 01 19:25:57 2023 Start Record command : Success Tue Aug 01 19:25:57 2023 Return status : 0 Tue Aug 01 19:26:03 2023 Record is completed Tue Aug 01 19:26:03 2023 Record stop is done successfully Tue Aug 01 19:38:33 2023 FPGA Configuration Command (req) Tue Aug 01 19:38:33 2023 FPGA Configuration command : Success Tue Aug 01 19:38:33 2023 Return status : 0 Tue Aug 01 19:38:33 2023 Configure Record Command (req) Tue Aug 01 19:38:33 2023 Configure Record command : Success Tue Aug 01 19:38:33 2023 Return status : 0 Tue Aug 01 19:38:33 2023 Read FPGA version Command (req) Tue Aug 01 19:38:33 2023 FPGA Version : 2.9 [Record] Tue Aug 01 19:38:40 2023 Start Record Command (req) Tue Aug 01 19:38:41 2023 Start Record command : Success Tue Aug 01 19:38:41 2023 Return status : 0 Tue Aug 01 19:38:46 2023 Record is completed Tue Aug 01 19:38:46 2023 Record stop is done successfully Tue Aug 01 19:58:15 2023 FPGA Configuration Command (req) Tue Aug 01 19:58:16 2023 FPGA Configuration command : Success Tue Aug 01 19:58:16 2023 Return status : 0 Tue Aug 01 19:58:16 2023 Configure Record Command (req) Tue Aug 01 19:58:16 2023 Configure Record command : Success Tue Aug 01 19:58:16 2023 Return status : 0 Tue Aug 01 19:58:16 2023 Read FPGA version Command (req) Tue Aug 01 19:58:16 2023 FPGA Version : 2.9 [Record] Tue Aug 01 19:58:20 2023 Start Record Command (req) Tue Aug 01 19:58:20 2023 Start Record command : Success Tue Aug 01 19:58:20 2023 Return status : 0 Tue Aug 01 19:58:50 2023 No LVDS data Tue Aug 01 19:58:50 2023 Record stop is done successfully Tue Aug 01 20:00:29 2023 FPGA Configuration Command (req) Tue Aug 01 20:00:30 2023 FPGA Configuration command : Success Tue Aug 01 20:00:30 2023 Return status : 0 Tue Aug 01 20:00:30 2023 Configure Record Command (req) Tue Aug 01 20:00:30 2023 Configure Record command : Success Tue Aug 01 20:00:30 2023 Return status : 0 Tue Aug 01 20:00:30 2023 Read FPGA version Command (req) Tue Aug 01 20:00:30 2023 FPGA Version : 2.9 [Record] Tue Aug 01 20:00:35 2023 Start Record Command (req) Tue Aug 01 20:00:35 2023 Start Record command : Success Tue Aug 01 20:00:35 2023 Return status : 0 Tue Aug 01 20:00:40 2023 Record is completed Tue Aug 01 20:00:40 2023 Record stop is done successfully Thu Aug 03 16:43:25 2023 Read DLL Verison Command (req) Thu Aug 03 16:43:25 2023 DLL Version : 1.0 Thu Aug 03 16:43:27 2023 FPGA Configuration Command (req) Thu Aug 03 16:43:28 2023 FPGA Configuration command : Success Thu Aug 03 16:43:28 2023 Return status : 0 Thu Aug 03 16:43:28 2023 Configure Record Command (req) Thu Aug 03 16:43:28 2023 Configure Record command : Success Thu Aug 03 16:43:28 2023 Return status : 0 Thu Aug 03 16:43:28 2023 Read FPGA version Command (req) Thu Aug 03 16:43:28 2023 FPGA Version : 2.9 [Record] Thu Aug 03 16:43:46 2023 Start Record Command (req) Thu Aug 03 16:43:46 2023 Start Record command : Success Thu Aug 03 16:43:46 2023 Return status : 0 Thu Aug 03 16:43:51 2023 Record is completed Thu Aug 03 16:43:51 2023 Record stop is done successfully Thu Aug 03 16:45:51 2023 Start Record Command (req) Thu Aug 03 16:45:52 2023 Start Record command : Success Thu Aug 03 16:45:52 2023 Return status : 0 Thu Aug 03 16:46:05 2023 Record is completed Thu Aug 03 16:46:05 2023 Record stop is done successfully Thu Aug 03 16:57:14 2023 Start Record Command (req) Thu Aug 03 16:57:14 2023 Start Record command : Success Thu Aug 03 16:57:14 2023 Return status : 0 Thu Aug 03 16:57:18 2023 Record is completed Thu Aug 03 16:57:18 2023 Record stop is done successfully Thu Aug 03 17:32:14 2023 FPGA Configuration Command (req) Thu Aug 03 17:32:14 2023 FPGA Configuration command : Success Thu Aug 03 17:32:14 2023 Return status : 0 Thu Aug 03 17:32:14 2023 Configure Record Command (req) Thu Aug 03 17:32:14 2023 Configure Record command : Success Thu Aug 03 17:32:14 2023 Return status : 0 Thu Aug 03 17:32:14 2023 Read FPGA version Command (req) Thu Aug 03 17:32:14 2023 FPGA Version : 2.9 [Record] Thu Aug 03 18:06:06 2023 Read DLL Verison Command (req) Thu Aug 03 18:06:06 2023 DLL Version : 1.0 Thu Aug 03 18:06:08 2023 FPGA Configuration Command (req) Thu Aug 03 18:06:08 2023 FPGA Configuration command : Success Thu Aug 03 18:06:08 2023 Return status : 0 Thu Aug 03 18:06:08 2023 Configure Record Command (req) Thu Aug 03 18:06:08 2023 Configure Record command : Success Thu Aug 03 18:06:08 2023 Return status : 0 Thu Aug 03 18:06:09 2023 Read FPGA version Command (req) Thu Aug 03 18:06:09 2023 FPGA Version : 2.9 [Record] Thu Aug 03 18:07:03 2023 Start Record Command (req) Thu Aug 03 18:07:03 2023 Start Record command : Success Thu Aug 03 18:07:03 2023 Return status : 0 Thu Aug 03 18:07:33 2023 No LVDS data Thu Aug 03 18:07:33 2023 Record stop is done successfully Thu Aug 03 18:08:07 2023 Start Record Command (req) Thu Aug 03 18:08:07 2023 Start Record command : Success Thu Aug 03 18:08:07 2023 Return status : 0 Thu Aug 03 18:08:12 2023 Record is completed Thu Aug 03 18:08:12 2023 Record stop is done successfully Thu Aug 03 18:13:26 2023 Start Record Command (req) Thu Aug 03 18:13:26 2023 Start Record command : Success Thu Aug 03 18:13:26 2023 Return status : 0 Thu Aug 03 18:13:34 2023 EEPROM Failure Thu Aug 03 18:13:55 2023 No LVDS data Thu Aug 03 18:13:55 2023 No Header Thu Aug 03 18:13:55 2023 Record stop is done successfully Thu Aug 03 18:14:43 2023 Start Record Command (req) Thu Aug 03 18:14:44 2023 Start Record command : Success Thu Aug 03 18:14:44 2023 Return status : 0 Thu Aug 03 18:16:04 2023 Record Process : Timeout Error! System disconnected Thu Aug 03 18:16:04 2023 Record stop is done successfully Thu Aug 03 18:16:41 2023 Start Record Command (req) Thu Aug 03 18:16:41 2023 Start Record command : Success Thu Aug 03 18:16:41 2023 Return status : 0 Thu Aug 03 18:18:01 2023 Record Process : Timeout Error! System disconnected Thu Aug 03 18:18:02 2023 Record stop is done successfully Thu Aug 03 18:18:46 2023 Start Record Command (req) Thu Aug 03 18:18:47 2023 Start Record command : Success Thu Aug 03 18:18:47 2023 Return status : 0 Thu Aug 03 18:20:07 2023 Record Process : Timeout Error! System disconnected Thu Aug 03 18:20:07 2023 Record stop is done successfully Thu Aug 03 18:20:38 2023 Start Record Command (req) Thu Aug 03 18:20:38 2023 Start Record command : Success Thu Aug 03 18:20:38 2023 Return status : 0 Thu Aug 03 18:21:58 2023 Record Process : Timeout Error! System disconnected Thu Aug 03 18:21:59 2023 Record stop is done successfully Thu Aug 03 18:22:16 2023 FPGA Configuration Command (req) Thu Aug 03 18:22:16 2023 FPGA Configuration command : Success Thu Aug 03 18:22:16 2023 Return status : 0 Thu Aug 03 18:22:16 2023 Configure Record Command (req) Thu Aug 03 18:22:16 2023 Configure Record command : Success Thu Aug 03 18:22:16 2023 Return status : 0 Thu Aug 03 18:22:16 2023 Read FPGA version Command (req) Thu Aug 03 18:22:16 2023 FPGA Version : 2.9 [Record] Thu Aug 03 18:22:22 2023 Start Record Command (req) Thu Aug 03 18:22:22 2023 Start Record command : Success Thu Aug 03 18:22:22 2023 Return status : 0 Thu Aug 03 18:22:28 2023 Record is completed Thu Aug 03 18:22:28 2023 Record stop is done successfully Thu Aug 03 18:23:04 2023 FPGA Configuration Command (req) Thu Aug 03 18:23:05 2023 FPGA Configuration command : Success Thu Aug 03 18:23:05 2023 Return status : 0 Thu Aug 03 18:23:05 2023 Configure Record Command (req) Thu Aug 03 18:23:05 2023 Configure Record command : Success Thu Aug 03 18:23:05 2023 Return status : 0 Thu Aug 03 18:23:05 2023 Read FPGA version Command (req) Thu Aug 03 18:23:05 2023 FPGA Version : 2.9 [Record] Thu Aug 03 18:23:11 2023 Start Record Command (req) Thu Aug 03 18:23:11 2023 Start Record command : Success Thu Aug 03 18:23:11 2023 Return status : 0 Thu Aug 03 18:23:26 2023 Record is completed Thu Aug 03 18:23:26 2023 Record stop is done successfully Thu Aug 03 18:24:41 2023 Start Record Command (req) Thu Aug 03 18:24:41 2023 Start Record command : Success Thu Aug 03 18:24:41 2023 Return status : 0 Thu Aug 03 18:25:02 2023 Record is completed Thu Aug 03 18:25:02 2023 Record stop is done successfully Thu Aug 03 19:40:00 2023 FPGA Configuration Command (req) Thu Aug 03 19:40:00 2023 FPGA Configuration command : Success Thu Aug 03 19:40:00 2023 Return status : 0 Thu Aug 03 19:40:00 2023 Configure Record Command (req) Thu Aug 03 19:40:00 2023 Configure Record command : Success Thu Aug 03 19:40:00 2023 Return status : 0 Thu Aug 03 19:40:00 2023 Read FPGA version Command (req) Thu Aug 03 19:40:00 2023 FPGA Version : 2.9 [Record] Thu Aug 03 19:40:06 2023 Start Record Command (req) Thu Aug 03 19:40:06 2023 Start Record command : Success Thu Aug 03 19:40:06 2023 Return status : 0 Thu Aug 03 19:40:33 2023 Record is completed Thu Aug 03 19:40:33 2023 Record stop is done successfully Fri Aug 04 17:55:15 2023 Read DLL Verison Command (req) Fri Aug 04 17:55:15 2023 DLL Version : 1.0 Fri Aug 04 17:55:17 2023 FPGA Configuration Command (req) Fri Aug 04 17:55:23 2023 Ethernet connection (req) Fri Aug 04 17:55:23 2023 Ethernet connection failed. [error -4051] Fri Aug 04 17:55:27 2023 FPGA Configuration : Timeout Error! System disconnected Fri Aug 04 17:55:27 2023 Return status : -5 Fri Aug 04 17:55:27 2023 Configure Record Command (req) Fri Aug 04 17:55:37 2023 Configure Record : Timeout Error! System disconnected Fri Aug 04 17:55:37 2023 Return status : -5 Fri Aug 04 17:55:37 2023 Read FPGA version Command (req) Fri Aug 04 17:55:47 2023 Unable to read FPGA Version. [error -5] Fri Aug 04 17:58:40 2023 Start Record Command (req) Fri Aug 04 17:58:50 2023 Start Record : Timeout Error! System disconnected Fri Aug 04 17:58:50 2023 Return status : -5 Fri Aug 04 17:59:37 2023 Start Record Command (req) Fri Aug 04 17:59:37 2023 Start Record command : Success Fri Aug 04 17:59:37 2023 Return status : 0 Fri Aug 04 18:00:06 2023 No LVDS data Fri Aug 04 18:00:06 2023 No Header Fri Aug 04 18:00:06 2023 Record stop is done successfully Fri Aug 04 18:00:14 2023 Start Record Command (req) Fri Aug 04 18:00:14 2023 Start Record command : Success Fri Aug 04 18:00:14 2023 Return status : 0 Fri Aug 04 18:00:43 2023 No LVDS data Fri Aug 04 18:00:43 2023 No Header Fri Aug 04 18:00:43 2023 Record stop is done successfully Fri Aug 04 18:00:48 2023 FPGA Configuration Command (req) Fri Aug 04 18:00:48 2023 FPGA Configuration command : Success Fri Aug 04 18:00:48 2023 Return status : 0 Fri Aug 04 18:00:48 2023 Configure Record Command (req) Fri Aug 04 18:00:48 2023 Configure Record command : Success Fri Aug 04 18:00:48 2023 Return status : 0 Fri Aug 04 18:00:48 2023 Read FPGA version Command (req) Fri Aug 04 18:00:48 2023 FPGA Version : 2.9 [Record] Fri Aug 04 18:00:55 2023 Start Record Command (req) Fri Aug 04 18:00:55 2023 Start Record command : Success Fri Aug 04 18:00:55 2023 Return status : 0 Fri Aug 04 18:01:01 2023 Record is completed Fri Aug 04 18:01:01 2023 Record stop is done successfully Fri Aug 04 18:03:48 2023 Read DLL Verison Command (req) Fri Aug 04 18:03:48 2023 DLL Version : 1.0 Fri Aug 04 18:03:50 2023 FPGA Configuration Command (req) Fri Aug 04 18:03:50 2023 FPGA Configuration command : Success Fri Aug 04 18:03:50 2023 Return status : 0 Fri Aug 04 18:03:50 2023 Configure Record Command (req) Fri Aug 04 18:03:50 2023 Configure Record command : Success Fri Aug 04 18:03:50 2023 Return status : 0 Fri Aug 04 18:03:51 2023 Read FPGA version Command (req) Fri Aug 04 18:03:51 2023 FPGA Version : 2.9 [Record] Fri Aug 04 18:03:56 2023 Start Record Command (req) Fri Aug 04 18:03:56 2023 Start Record command : Success Fri Aug 04 18:03:56 2023 Return status : 0 Fri Aug 04 18:04:00 2023 Record is completed Fri Aug 04 18:04:00 2023 Record stop is done successfully Thu Aug 10 18:26:04 2023 Read DLL Verison Command (req) Thu Aug 10 18:26:04 2023 DLL Version : 1.0 Thu Aug 10 18:26:46 2023 FPGA Configuration Command (req) Thu Aug 10 18:26:56 2023 FPGA Configuration : Timeout Error! System disconnected Thu Aug 10 18:26:56 2023 Return status : -5 Thu Aug 10 18:26:56 2023 Configure Record Command (req) Thu Aug 10 18:27:06 2023 Configure Record : Timeout Error! System disconnected Thu Aug 10 18:27:06 2023 Return status : -5 Thu Aug 10 18:27:06 2023 Read FPGA version Command (req) Thu Aug 10 18:27:16 2023 Unable to read FPGA Version. [error -5] Thu Aug 10 18:44:14 2023 FPGA Configuration Command (req) Thu Aug 10 18:44:24 2023 FPGA Configuration : Timeout Error! System disconnected Thu Aug 10 18:44:24 2023 Return status : -5 Thu Aug 10 18:44:24 2023 Configure Record Command (req) Thu Aug 10 18:44:34 2023 Configure Record : Timeout Error! System disconnected Thu Aug 10 18:44:34 2023 Return status : -5 Thu Aug 10 18:44:34 2023 Read FPGA version Command (req) Thu Aug 10 18:44:44 2023 Unable to read FPGA Version. [error -5] Wed Aug 16 13:05:30 2023 Read DLL Verison Command (req) Wed Aug 16 13:05:30 2023 DLL Version : 1.0 Wed Aug 16 15:36:52 2023 Read DLL Verison Command (req) Wed Aug 16 15:36:52 2023 DLL Version : 1.0 Wed Aug 16 15:36:55 2023 FPGA Configuration Command (req) Wed Aug 16 15:36:55 2023 FPGA Configuration command : Success Wed Aug 16 15:36:55 2023 Return status : 0 Wed Aug 16 15:36:55 2023 Configure Record Command (req) Wed Aug 16 15:36:55 2023 Configure Record command : Success Wed Aug 16 15:36:55 2023 Return status : 0 Wed Aug 16 15:36:55 2023 Read FPGA version Command (req) Wed Aug 16 15:36:55 2023 FPGA Version : 2.9 [Record] Wed Aug 16 15:37:19 2023 Start Record Command (req) Wed Aug 16 15:37:19 2023 Start Record command : Success Wed Aug 16 15:37:19 2023 Return status : 0 Wed Aug 16 15:37:25 2023 Record is completed Wed Aug 16 15:37:25 2023 Record stop is done successfully Wed Aug 16 16:20:59 2023 FPGA Configuration Command (req) Wed Aug 16 16:21:00 2023 FPGA Configuration command : Success Wed Aug 16 16:21:00 2023 Return status : 0 Wed Aug 16 16:21:00 2023 Configure Record Command (req) Wed Aug 16 16:21:00 2023 Configure Record command : Success Wed Aug 16 16:21:00 2023 Return status : 0 Wed Aug 16 16:21:00 2023 Read FPGA version Command (req) Wed Aug 16 16:21:00 2023 FPGA Version : 2.9 [Record] Wed Aug 16 16:21:06 2023 Start Record Command (req) Wed Aug 16 16:21:06 2023 Start Record command : Success Wed Aug 16 16:21:06 2023 Return status : 0 Wed Aug 16 16:21:11 2023 Record is completed Wed Aug 16 16:21:11 2023 Record stop is done successfully