Wed Sep 21 17:02:41 2022
Read DLL Verison Command (req)

Wed Sep 21 17:02:41 2022
DLL Version : 1.0

Wed Sep 21 17:02:46 2022
Reset FPGA Command (req)

Wed Sep 21 17:02:46 2022
Reset FPGA command : Success

Wed Sep 21 17:02:46 2022
Return status : 0

Wed Sep 21 17:02:46 2022
Configure Record Command (req)

Wed Sep 21 17:02:46 2022
Configure Record command : Success

Wed Sep 21 17:02:46 2022
Return status : 0

Wed Sep 21 17:02:46 2022
Read FPGA version Command (req)

Wed Sep 21 17:02:46 2022

FPGA Version : 2.8 [Record]


Wed Sep 21 17:02:53 2022
FPGA Configuration Command (req)

Wed Sep 21 17:02:53 2022
FPGA Configuration command : Success

Wed Sep 21 17:02:53 2022
Return status : 0

Wed Sep 21 17:02:54 2022
Configure Record Command (req)

Wed Sep 21 17:02:54 2022
Configure Record command : Success

Wed Sep 21 17:02:54 2022
Return status : 0

Wed Sep 21 17:02:54 2022
Read FPGA version Command (req)

Wed Sep 21 17:02:54 2022

FPGA Version : 2.8 [Record]


Wed Sep 21 17:03:13 2022
Start Record Command (req)

Wed Sep 21 17:03:13 2022
Start Record command : Success

Wed Sep 21 17:03:13 2022
Return status : 0

Wed Sep 21 17:03:43 2022
No LVDS data

Wed Sep 21 17:03:43 2022
Record stop is done successfully

Wed Sep 21 17:05:32 2022
Start Record Command (req)

Wed Sep 21 17:05:42 2022
Start Record : 
Timeout Error! System disconnected

Wed Sep 21 17:05:42 2022
Return status : -5

Wed Sep 21 17:06:01 2022
Start Record Command (req)

Wed Sep 21 17:06:01 2022
Start Record command : Success

Wed Sep 21 17:06:01 2022
Return status : 0

Wed Sep 21 17:06:31 2022
No LVDS data

Wed Sep 21 17:06:31 2022
Record stop is done successfully

Wed Sep 21 17:06:51 2022
Read DLL Verison Command (req)

Wed Sep 21 17:06:51 2022
DLL Version : 1.0

Wed Sep 21 17:06:59 2022
Start Record Command (req)

Wed Sep 21 17:07:00 2022
Start Record command : Success

Wed Sep 21 17:07:00 2022
Return status : 0

Wed Sep 21 17:07:30 2022
No LVDS data

Wed Sep 21 17:07:30 2022
Record stop is done successfully

Wed Sep 21 17:15:24 2022
Read DLL Verison Command (req)

Wed Sep 21 17:15:24 2022
DLL Version : 1.0

Wed Sep 21 17:15:27 2022
Reset FPGA Command (req)

Wed Sep 21 17:15:27 2022
Reset FPGA command : Success

Wed Sep 21 17:15:27 2022
Return status : 0

Wed Sep 21 17:15:27 2022
FPGA Configuration Command (req)

Wed Sep 21 17:15:27 2022
FPGA Configuration command : Success

Wed Sep 21 17:15:27 2022
Return status : 0

Wed Sep 21 17:15:27 2022
Configure Record Command (req)

Wed Sep 21 17:15:27 2022
Configure Record command : Success

Wed Sep 21 17:15:27 2022
Return status : 0

Wed Sep 21 17:15:27 2022
Read FPGA version Command (req)

Wed Sep 21 17:15:27 2022

FPGA Version : 2.8 [Record]


Wed Sep 21 17:15:41 2022
Start Record Command (req)

Wed Sep 21 17:15:41 2022
Start Record command : Success

Wed Sep 21 17:15:41 2022
Return status : 0

Wed Sep 21 17:16:11 2022
No LVDS data

Wed Sep 21 17:16:11 2022
Record stop is done successfully

Wed Sep 21 17:21:51 2022
Read DLL Verison Command (req)

Wed Sep 21 17:21:51 2022
DLL Version : 1.0

Wed Sep 21 17:21:55 2022
FPGA Configuration Command (req)

Wed Sep 21 17:21:55 2022
FPGA Configuration command : Success

Wed Sep 21 17:21:55 2022
Return status : 0

Wed Sep 21 17:21:55 2022
Configure Record Command (req)

Wed Sep 21 17:21:55 2022
Configure Record command : Success

Wed Sep 21 17:21:55 2022
Return status : 0

Wed Sep 21 17:21:55 2022
Read FPGA version Command (req)

Wed Sep 21 17:21:55 2022

FPGA Version : 2.8 [Record]


Wed Sep 21 17:28:33 2022
Start Record Command (req)

Wed Sep 21 17:28:33 2022
Start Record command : Success

Wed Sep 21 17:28:33 2022
Return status : 0

Wed Sep 21 17:29:02 2022
No LVDS data

Wed Sep 21 17:29:02 2022
No Header

Wed Sep 21 17:29:02 2022
Record stop is done successfully

Wed Sep 21 17:29:09 2022
Read DLL Verison Command (req)

Wed Sep 21 17:29:09 2022
DLL Version : 1.0

Wed Sep 21 17:29:11 2022
FPGA Configuration Command (req)

Wed Sep 21 17:29:11 2022
FPGA Configuration command : Success

Wed Sep 21 17:29:11 2022
Return status : 0

Wed Sep 21 17:29:11 2022
Configure Record Command (req)

Wed Sep 21 17:29:11 2022
Configure Record command : Success

Wed Sep 21 17:29:11 2022
Return status : 0

Wed Sep 21 17:29:11 2022
Read FPGA version Command (req)

Wed Sep 21 17:29:11 2022

FPGA Version : 2.8 [Record]


Wed Sep 21 17:30:16 2022
Start Record Command (req)

Wed Sep 21 17:30:16 2022
Start Record command : Success

Wed Sep 21 17:30:16 2022
Return status : 0

Wed Sep 21 17:30:46 2022
No LVDS data

Wed Sep 21 17:30:46 2022
Record stop is done successfully

Wed Sep 21 17:31:10 2022
Read DLL Verison Command (req)

Wed Sep 21 17:31:10 2022
DLL Version : 1.0

Wed Sep 21 17:31:25 2022
FPGA Configuration Command (req)

Wed Sep 21 17:31:25 2022
FPGA Configuration command : Success

Wed Sep 21 17:31:25 2022
Return status : 0

Wed Sep 21 17:31:25 2022
Configure Record Command (req)

Wed Sep 21 17:31:25 2022
Configure Record command : Success

Wed Sep 21 17:31:25 2022
Return status : 0

Wed Sep 21 17:31:25 2022
Read FPGA version Command (req)

Wed Sep 21 17:31:25 2022

FPGA Version : 2.8 [Record]


Wed Sep 21 17:31:34 2022
Start Record Command (req)

Wed Sep 21 17:31:34 2022
Start Record command : Success

Wed Sep 21 17:31:34 2022
Return status : 0

Wed Sep 21 17:32:04 2022
No LVDS data

Wed Sep 21 17:32:04 2022
Record stop is done successfully

Wed Sep 21 17:33:21 2022
Start Record Command (req)

Wed Sep 21 17:33:21 2022
Start Record command : Success

Wed Sep 21 17:33:21 2022
Return status : 0

Wed Sep 21 17:33:51 2022
No LVDS data

Wed Sep 21 17:33:51 2022
Record stop is done successfully

Wed Sep 21 17:38:36 2022
FPGA Configuration Command (req)

Wed Sep 21 17:38:36 2022
FPGA Configuration command : Success

Wed Sep 21 17:38:36 2022
Return status : 0

Wed Sep 21 17:38:36 2022
Read FPGA version Command (req)

Wed Sep 21 17:38:36 2022

FPGA Version : 2.8 [Record]


Wed Sep 21 17:38:36 2022
FPGA Configuration Command (req)

Wed Sep 21 17:38:36 2022
FPGA Configuration command : Success

Wed Sep 21 17:38:36 2022
Return status : 0

Wed Sep 21 17:38:37 2022
FPGA Configuration Command (req)

Wed Sep 21 17:38:37 2022
FPGA Configuration command : Success

Wed Sep 21 17:38:37 2022
Return status : 0

Wed Sep 21 17:38:37 2022
Configure Record Command (req)

Wed Sep 21 17:38:37 2022
Configure Record command : Success

Wed Sep 21 17:38:37 2022
Return status : 0

Mon Sep 26 13:27:16 2022
Read DLL Verison Command (req)

Mon Sep 26 13:27:16 2022
DLL Version : 1.0

Mon Sep 26 13:27:20 2022
FPGA Configuration Command (req)

Mon Sep 26 13:27:30 2022
FPGA Configuration : 
Timeout Error! System disconnected

Mon Sep 26 13:27:30 2022
Return status : -5

Mon Sep 26 13:27:30 2022
Configure Record Command (req)

Mon Sep 26 13:27:30 2022
Configure Record command : Success

Mon Sep 26 13:27:30 2022
Return status : 0

Mon Sep 26 13:27:30 2022
Read FPGA version Command (req)

Mon Sep 26 13:27:30 2022

FPGA Version : 2.8 [Record]


Mon Sep 26 13:28:49 2022
Start Record Command (req)

Mon Sep 26 13:28:49 2022
Start Record command : Success

Mon Sep 26 13:28:49 2022
Return status : 0

Mon Sep 26 13:29:18 2022
No LVDS data

Mon Sep 26 13:29:18 2022
No Header

Mon Sep 26 13:29:18 2022
Record stop is done successfully