sep=;
Name;Value
illum_p_dis_pol;False (Inacive level is 0)
lvds_pll_lock_intr_dis;False
freq_ratio;2730
cos_f1_q3_coeff;0
master_pll_lock;True
blk_blank_size;0
op_clk_edge;False (Falling edge)
cos_f1_q2_coeff;-32767
vd_pol;True (active high)
sin_f2_q3_coeff;0
phase_lin_corr_en;False
tillum_slv_addr;114
op_cs_pol;True (active high)
scratch2;143
phase_aux_pol;True (active high)
padding_en;False
sin_f2_q4_coeff;28377
cos_f2_q0_coeff;32767
master_pll_lock_intr_dis;False
frm_trailer_en;False
mod_pll_update;False
sin_f1_q4_coeff;0
coeff_illum;0
scratch3;0
illum_en_early;False (synced)
row_end;239
sin_f1_q5_coeff;0
ddr_controller_intr_dis;False
sscg_modulation;0
sscg_period;0
mod_m2;15
comp_mod_ref_inv;3
filt_scale;0
mod_m1;20
tsensor_calib;39
easy_conf_en;True
sin_f2_q0_coeff;0
normal_frm_intg_scale;0
op_data_arrange_mode;2 (rearrange_8)
cols_to_merge;1
amplitude_threshold;1
filt_coeff_y_re_f2;0
phase_corr_2;581
phase_corr_1;599
filt_coeff_y_re_f1;0
op_overflow;False
init_3;0
init_2;0
init_5;0
phase_lin_coeff0_10;0
lvds_pll_lock;True
vco_freq2;360.00MHz
standby_pin_en;False
sin_f1_q1_coeff;32767
vco_freq1;480.00MHz
filt_coeff_x_re_f2;0
filt_coeff_x_re_f1;0
mod_m_frac1;0
sin_f1_q3_coeff;-32767
blk_size;1024
ddr_controller_flag;True
sysclk_in_freq;0 (48)
output_mode;0 (depth data)
frame_sync_delay;1
illum_mod_early;False (synced)
sin_f2_q5_coeff;-28377
disable_offset_corr;False
illum_ovtemp_intr_dis;False
fb_ready_pol;True (active_high)
op_underflow_intr_dis;False
phase_lin_corr_period;0 (90)
dealiased_ph_mask;3
filt_coeff_y_im_f1;0
sscg_en;False
filt_coeff_y_im_f2;0
mod_freq2;60.00MHz
mod_freq1;40.00MHz
illum_fb_inv;0
mod_ps2;0
phase_corr_add;False (Subtract Correction)
quad_hop_en;False
phase_lin_coeff0_5;0
hdr_scale;0
ramp_pat;1 (Row ramp)
coeff_sensor;0
cos_f2_q4_coeff;-16384
sin_f2_q1_coeff;28377
phase_lin_coeff1_8;0
fb_ready_en;True (enable)
minor;30
fb_error_cnt_threshold;10
cos_f1_q5_coeff;0
op_serial_width;False (1-lane serial mode)
delay_fb_dc_corr_mode;1
debug_frame_number_en;False
blk_header_en;False
intg_time;8%
intg_duty_cycle_set_failed;False
row_start;0
phase_lin_coeff1_15;0
phase_lin_coeff1_14;0
phase_lin_coeff1_13;0
phase_lin_coeff1_12;0
phase_lin_coeff1_11;0
cos_f1_q1_coeff;0
phase_lin_coeff0_14;0
phase_lin_coeff0_15;0
mod_m_frac2;0
phase_lin_coeff0_11;0
phase_lin_coeff0_12;0
quad_hop_offset2;0
frm_header_en;False
cos_f2_q3_coeff;32767
illum_fb_error_cnt;0
hdr_phase_corr_2;0
major;0
filt_coeff_x_im_f1;0
filt_coeff_x_im_f2;0
illum_n_dis_pol;False (Inactive level is 1)
illum_current;163mA
hdr_phase_corr_1;0
demod_static_pol;False (Hold low)
cos_f1_q0_coeff;32767
mod_n2;2
mod_n1;2
tillum_calib;31
init_4;False
iq_scale;0
pvdd;3300mV
tg_dis;False
quad_hop_offset1;0
phase_lin_coeff0_13;0
sync_mode;False
bin_col_count;320
cos_f2_q2_coeff;-16384
sensor_ovtemp_thresh;100
mac_test_enable;False
calib_prec;False (1)
illum_power;8800mW
sin_f1_q2_coeff;0
comp_fb_error_cnt;0
phase_lin_coeff1_7;0
phase_lin_coeff1_6;0
phase_lin_coeff1_5;0
phase_lin_coeff1_4;0
phase_lin_coeff1_3;0
phase_lin_coeff1_2;0
phase_lin_coeff1_1;0
phase_lin_coeff1_0;0
dealias_16bit_op_enable;False
shutter_dis;False
phase_lin_coeff1_9;0
binning_en;True
fe_last_cycle;False (Frame end is asserted one cycle after the last byte)
unambiguous_range;4m
ma;2
mb;3
disable_temp_corr;False
ddr_calibration_intr_dis;False
phy_test_enable;False
col_start;0
sin_f2_q2_coeff;-28377
standby;False
amplitude_scale;0
sub_frame_cnt_max;4 (4)
mod_ps1;1
col_end;19
tillum;39
mix_volt;1500mV
op_overflow_intr_dis;False
ind_freq_data_en;False
standby_pin_pol;False (active low)
phase_aux_en;False (disable)
intg_duty_cycle;5
op_clk_freq;1 (12)
pix_cnt_max;133333
illum_static_pol;False (Hold low)
modulation_hold;False
scratch1;4
cos_f2_q1_coeff;-16384
slave_mode;False
data_latency;3
phase_lin_coeff1_10;0
amplitude_post_scale;0
op_underflow;False
sensor_ovtemp_intr_dis;False
illum_power_percentage;100%
blk_blank_skip;0
fe_pol;True (active high)
delay_fb_corr_mode;1
cos_f1_q4_coeff;0
software_reset;False
frequency_scale;12
main_current;242mA
vd_active;8
delay_fb_coeff_1;2560
col_rdout_dir;True (count down)
dealias_en;True
phase_lin_coeff0_8;0
phase_lin_coeff0_9;0
phase_lin_coeff0_6;0
phase_lin_coeff0_7;0
pixel_data_size;4 (4 bytes)
bin_row_count;240
phase_lin_coeff0_2;0
phase_lin_coeff0_3;0
phase_lin_coeff0_0;0
phase_lin_coeff0_1;0
phase_lin_coeff0_4;0
frm_blank_size;0
quad_cnt_max;6 (6)
ddr_calibration_flag;True
rows_to_merge;1
device;True (Gen2)
pix_cnt_max_set_failed;False
filt_en;False
op_mode;0 (DVP Mode)
kb;1
ka;2
cos_f2_q5_coeff;-16384
tsensor;46
illum_ovtemp_thresh;90
sin_f1_q0_coeff;0
comp_vref;1397mV
saturation_threshold;0
hd_pol;True (active high)
ind_freq_data_sel;False (freq1 data)