RSS_CSI2A RSS CSI2A Module Registers [0 ... 99] CSI2_REVISION 0x00000030 MODULE REVISION This register contains the IP revision code in binary coded digital. For example we have: 0x01 = revision 0.1 and 0x21 = revision 2.1 [Memory Mapped] CSI2_SYSCONFIG 0x00000001 SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register. [Memory Mapped] CSI2_SYSSTATUS 0x00000001 SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register. [Memory Mapped] CSI2_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt. The context shall be enabled for events to be generated on that context. If the [Memory Mapped] CSI2_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually. [Memory Mapped] CSI2_CTRL 0x00000000 GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified dynamically (except IF_EN bit field). [Memory Mapped] CSI2_DBG_H 0x00000000 DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The register is [Memory Mapped] CSI2_GNQ 0x0000001B GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design. [Memory Mapped] CSI2_COMPLEXIO_CFG2 0x00000000 COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in addit [Memory Mapped] CSI2_COMPLEXIO_CFG1 0x00000000 COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in additi [Memory Mapped] CSI2_COMPLEXIO1_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - All errors from complex IO #1 [Memory Mapped] CSI2_COMPLEXIO2_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - All errors from complex IO #2 [Memory Mapped] CSI2_SHORT_PACKET 0x00000000 SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F [Memory Mapped] CSI2_COMPLEXIO1_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - All errors from complex IO #1 [Memory Mapped] CSI2_COMPLEXIO2_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - All errors from complex IO #2 [Memory Mapped] CSI2_DBG_P 0x00000000 DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module. The debug mode is enabled by CSI2_CTRL.DBG_EN. Only full 32-bit values shall be written. The register is [Memory Mapped] CSI2_TIMING 0x7FFF7FFF TIMING REGISTER This register controls the CSI2 RECEIVER module. This register shall not be modified while CSI2_CTRL.IF_EN is set to '1'. It is used to indicate the number of L3 cycles for the Stop State monitoring. [Memory Mapped] CSI2_CTX0_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX0_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX0_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX0_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX0_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX0_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX0_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX0_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX1_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX1_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX1_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX1_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX1_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX1_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX1_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX1_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX2_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX2_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX2_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX2_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX2_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX2_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX2_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX2_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX3_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX3_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX3_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX3_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX3_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX3_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX3_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX3_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX4_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX4_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX4_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX4_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX4_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX4_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX4_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX4_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX5_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX5_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX5_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX5_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX5_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX5_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX5_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX5_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX6_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX6_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX6_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX6_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX6_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX6_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX6_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX6_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX7_CTRL1 0x00010008 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_CTX7_CTRL2 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code (except for VIRTUAL_ID and FORMAT fields). The change of VIRTUIAL_ID and FORMAT ha [Memory Mapped] CSI2_CTX7_DAT_OFST 0x00000000 DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory. This register applies for both CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR. [Memory Mapped] CSI2_CTX7_DAT_PING_ADDR 0x00000000 DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PING address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX7_DAT_PONG_ADDR 0x00000000 DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored. The destination is double buffered: this register sets the PONG address. Double buffering is enabled when the addresses [Memory Mapped] CSI2_CTX7_IRQENABLE 0x00000000 INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX7_IRQSTATUS 0x00000000 INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context. [Memory Mapped] CSI2_CTX7_CTRL3 0x00000000 CONTROL REGISTER - Context This register controls the Context. This register is shadowed: modifications are taken into account after the next FSC sync code. [Memory Mapped] CSI2_PHY_CFG_REG0 0x00000000 Memory Mapped CSI2_PHY_CFG_REG1 0x00000000 Memory Mapped CSI2_PHY_CFG_REG2 0x00000000 Memory Mapped CSI2_PHY_CFG_REG3 0x00000000 Memory Mapped CSI2_PHY_CFG_REG4 0x00000000 Memory Mapped CSI2_PHY_CFG_REG5 0x00000000 Memory Mapped CSI2_PHY_CFG_REG6 0x00000000 Memory Mapped CSI2_CTX0_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX0_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX1_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX1_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX2_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX2_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX3_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX3_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX4_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX4_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX5_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX5_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] [100 ... 103] CSI2_CTX6_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX6_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped] CSI2_CTX7_TRANSCODEH 0x00000000 Transcode configuration register: defines horizontal frame cropping [Memory Mapped] CSI2_CTX7_TRANSCODEV 0x00000000 Transcode configuration register: defines vertical frame cropping [Memory Mapped]