; .mmregs


         .include "lpva200.inc"


       .def    _pwr_enterIdleCfg1
       .def    _pwr_enterIdleCfg2
       .def    _pwr_enterIdleCfg3
       .text

        ; precondition that interrupts must already be disabled
        ; This is the lowest power idle configuration where everything is idled and the SYSCLKDIS (System Clock Disable) bit is set
        ; The following events can get us out of idle configuration 2:
        ; RTC interrupt
        ; External wakeup pin interrupt
        ; DSP reset
_pwr_enterIdleCfg3:
	    ; bit(ST1, #11) = #1		; Disable interrupts (done before this routine)
		; Idle peripherals clock gating control
        *port(#IDLE_PCGCR) = #(MASTER_CLK_DIS | RESERVED_PCGCR)
        *port(#IDLE_PCGCR_MSW) = #(  LCD_IDLE | SARADC_IDLE | USB_IDLE | DMA1_IDLE | DMA2_IDLE | DMA3_IDLE | ANAREG_IDLE | RESERVED_PCGCR_MSW)
        
        repeat(#(6-1))
        nop 
        .if 0
        ; Select which power domain Idle Domains in the DSP 
        ; Per section 8 of SPRU317j 
        ; Per section SPRUFX5
        ; when XPORT idle then CPU must be idled
        ; at this time there are no peripherals active so idle everything
        *port(#IDLE_ICR) = #(IPORT_IDLE | DPORT_IDLE | HWA_IDLE | MPORT_IDLE | CPU_IDLE | XPORT_IDLE | CLK_IDLE | RESERVED_ICR) 
        
        repeat(#(6-1))
        nop
        ; The idle instruction forces the program being executed to wait until 
        ; an interrupt or a reset occurs
        idle
		repeat(#(6-1)) ; Repeat the instruction that follows the #() times + 1
        nop	
        ; Manually enable the MPORT
        *port(#IDLE_ICR) = #( HWA_IDLE | RESERVED_ICR)
        idle                    ; apply new idle configuration (Note. Does not put CPU into idle)
		; bit(ST1, #11) = #0		; Enable interrupts	
		.endif
		return

		.if 1
        ; precondition that interrupts must already be disabled
        ; Next Lowest power (Master Clock is still left running, with everything idle)
        ; The following events can get us out of idle configuration 2:
        ; RTC interrupt
        ; External wakeup pin interrupt
        ; DSP reset
_pwr_enterIdleCfg2:
		; bit(ST1, #11) = #1		; Disable interrupts
		; Idle peripherals clock gating control
        *port(#IDLE_PCGCR) = #(IIS3_IDLE | SPI_IDLE | UART_IDLE | DMA0_IDLE | MMCSD0_IDLE | COPROC_IDLE | MMCSD1_IDLE | IIS0_IDLE | IIS1_IDLE | TIMER0_IDLE | EMIF_IDLE | TIMER1_IDLE | TIMER2_IDLE | IIS2_IDLE |  RESERVED_PCGCR)
        *port(#IDLE_PCGCR_MSW) = #(  LCD_IDLE | SARADC_IDLE | USB_IDLE | DMA1_IDLE | DMA2_IDLE | DMA3_IDLE | ANAREG_IDLE | RESERVED_PCGCR_MSW)
        ; Select which power domain Idle Domains in the DSP 
        ; Per section 8 of SPRU317j 
        ; Per section SPRUFX5
        ; when XPORT idle then CPU must be idled
        ; at this time there are no peripherals active so idle everything
        *port(#IDLE_ICR) = #(IPORT_IDLE | DPORT_IDLE | HWA_IDLE | MPORT_IDLE | CPU_IDLE | XPORT_IDLE | CLK_IDLE | RESERVED_ICR) 
        
        repeat(#(6-1))
        nop
        ; The idle instruction forces the program being executed to wait until 
        ; an interrupt or a reset occurs
        idle
		repeat(#(6-1)) ; Repeat the instruction that follows the #() times + 1
        nop	
        ; Manually enable the MPORT
        *port(#IDLE_ICR) = #( HWA_IDLE | RESERVED_ICR)
        idle                    ; apply new idle configuration (Note. Does not put CPU into idle)
		; bit(ST1, #11) = #0		; Enable interrupts	
		return
		.endif		
		
		
		; precondition that interrupts must already be disabled
		; Idles all unused peripherals and idles the CPU
_pwr_enterIdleCfg1:
		;bit(ST1, #11) = #1		; Disable interrupts
		; Idle peripherals clock gating control
		; Leave the following active (Not Idle):
		; i2S2 (aka iiS2) which uses DMA1 controller  -Used to receive data from the gateware
		; i2c  (akd iic)  which uses DMA2 controller
        *port(#IDLE_PCGCR) = #(IIS3_IDLE | SPI_IDLE | UART_IDLE | DMA0_IDLE | MMCSD0_IDLE | COPROC_IDLE | MMCSD1_IDLE | IIS0_IDLE | IIS1_IDLE | TIMER0_IDLE | EMIF_IDLE | TIMER1_IDLE | TIMER2_IDLE | RESERVED_PCGCR)
        *port(#IDLE_PCGCR_MSW) = #( LCD_IDLE | SARADC_IDLE  | USB_IDLE |  DMA3_IDLE | ANAREG_IDLE | RESERVED_PCGCR_MSW)
        
        ; Select which power domain Idle Domains in the DSP 
        ; Per section 8 of SPRU317j 
        ; Per section SPRUFX5
        ; Note when XPORT idle then CPU must be idled
        ; Leave the following active (Not Idle):
        ; MPORT_IDLE for DMA activity
        *port(#IDLE_ICR) = #(IPORT_IDLE | DPORT_IDLE | XPORT_IDLE |  HWA_IDLE | CPU_IDLE | CLK_IDLE | RESERVED_ICR) 
        
        repeat(#(6-1))
        nop
        ; The idle instruction forces the program being executed to wait until 
        ; an interrupt or a reset occurs
        idle
		repeat(#(6-1)) ; Repeat the instruction that follows the #() times + 1
        nop	
		;bit(ST1, #11) = #0		; Enable interrupts	
		return		
			
	    .end