; General settings that can be overwritten in the host code
; that calls the AISGen library.
[General]

; Can be 8 or 16 - used in emifa
busWidth=16

; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW0
BootMode=EMIFA

; 8,16,24 - used for SPI,I2C
;AddrWidth=8          

; NO_CRC,SECTION_CRC,SINGLE_CRC
crcCheckType=NO_CRC


; This section allows setting the PLL0 system clock with a  
; specified multiplier and divider as shown. The clock source
; can also be chosen for internal or external.
;           |------24|------16|-------8|-------0|
; PLL0CFG0: | CLKMODE| PLLM   | PREDIV | POSTDIV|
; PLL0CFG1: | RSVD   | PLLDIV1| PLLDIV3| PLLDIV7|
; PLL0CFG0: | 0      |   25   |   1    |    2   |
; PLL0CFG1: | 0      |   1    |   12   |   6    |
;[PLL0CONFIG]
;PLL0CFG0 = 0x00180001
;PLL0CFG1 = 0x00000205
[PLL0CONFIG]
PLL0CFG0 = 0x00180001
;PLL0CFG0 = 0x00180101	;was
PLL0CFG1 = 0x00000B05

;PERIPHCLKCFG = 0x00010064





; This section lets us configure the peripheral interface
; of the current booting peripheral (I2C, SPI, or UART).
; Use with caution. The format of the PERIPHCLKCFG field 
; is as follows:
; SPI:        |------24|------16|-------8|-------0|
;             |           RSVD           |PRESCALE|
;
; I2C:        |------24|------16|-------8|-------0|
;             |  RSVD  |PRESCALE|  CLKL  |  CLKH  |
;
; UART:       |------24|------16|-------8|-------0|
;             | RSVD   |  OSR   |  DLH   |  DLL   |
;[PERIPHCLKCFG]
;PERIPHCLKCFG = 0x00000000





; This section can be used to configure the async chip selects
; of the EMIFA (CS2-CS5).  The fields required to do this
; are given below.
;           |------24|------16|-------8|-------0|
; A1CR:     |                A1CR               |
; A2CR:     |                A2CR               |
; A3CR:     |                A3CR               |
; A4CR:     |                A4CR               |
; NANDFCR:  |              NANDFCR              |
;[EMIF25ASYNC]
;A1CR = 0x00000000
A2CR = 0x3FFFFFFD
;A3CR = 0x00000000
;A4CR = 0x00000000
;NANDFCR = 0x00000000




; This section allows setting up the PLL1. Usually this will 
; take place as part of the EMIF3a DDR setup. The format of
; the input args is as follows:
;           |------24|------16|-------8|-------0|
; PLL1CFG0: |    PLLM| POSTDIV| PLLDIV1| PLLDIV2|
; PLL1CFG1: |           RSVD           | PLLDIV3|
; PLL1CFG0: |    25  |  2     | 1      | 1      |
; PLL1CFG1: |           RSVD           | 1      |
;[PLL1CONFIG]

[PLL1CONFIG]
PLL1CFG0 = 0x18010001 
PLL1CFG1 = 0x00000002

;DSMP DDR2 
[DSP_EMIF3DDR_PATCHFXN]
DDRPHYC1R = 0x00000084
SDCR = 0x0093c622
SDTIMR = 0x1E922A09
SDTIMR2 = 0x8412C722
SDRCR = 0xC0000249
CLK2XSRC = 0x00000000