//- 15.6 inch, For 1366 x 768
/*Dmesg from kernel*/
jht_8mq:/ # dmesg |grep DSI84-I2C
[    2.786214] DSI84-I2C: read 0x00  - 0x35
[    2.787145] DSI84-I2C: read 0x0d  - 0x00
[    2.788075] DSI84-I2C: read 0x0a  - 0x05
[    2.789012] DSI84-I2C: read 0x0b  - 0x10
[    2.789946] DSI84-I2C: read 0x10  - 0x20
[    2.790875] DSI84-I2C: read 0x18  - 0x78
[    2.791805] DSI84-I2C: read 0x1a  - 0x03
[    2.792749] DSI84-I2C: read 0x20  - 0x56
[    2.793680] DSI84-I2C: read 0x21  - 0x05
[    2.794614] DSI84-I2C: read 0x22  - 0x00
[    2.795547] DSI84-I2C: read 0x23  - 0x00
[    2.796479] DSI84-I2C: read 0x24  - 0x00
[    2.797407] DSI84-I2C: read 0x25  - 0x03
[    2.798329] DSI84-I2C: read 0x26  - 0x00
[    2.799249] DSI84-I2C: read 0x27  - 0x00
[    2.800170] DSI84-I2C: read 0x28  - 0x21
[    2.800866] DSI84-I2C: read 0x29  - 0x00
[    2.801798] DSI84-I2C: read 0x2a  - 0x00
[    2.802729] DSI84-I2C: read 0x2b  - 0x00
[    2.803662] DSI84-I2C: read 0x2c  - 0x00
[    2.804595] DSI84-I2C: read 0x2d  - 0x00
[    2.805528] DSI84-I2C: read 0x2e  - 0x00
[    2.806459] DSI84-I2C: read 0x2f  - 0x00
[    2.807392] DSI84-I2C: read 0x30  - 0x00
[    2.808321] DSI84-I2C: read 0x31  - 0x00
[    2.809250] DSI84-I2C: read 0x32  - 0x00
[    2.810173] DSI84-I2C: read 0x33  - 0x00
[    2.811093] DSI84-I2C: read 0x34  - 0xc8
[    2.812017] DSI84-I2C: read 0x35  - 0x00
[    2.812870] DSI84-I2C: read 0x36  - 0x00
[    2.813790] DSI84-I2C: read 0x37  - 0x00
[    2.814710] DSI84-I2C: read 0x38  - 0xc8
[    2.815631] DSI84-I2C: read 0x39  - 0x00
[    2.816554] DSI84-I2C: read 0x3a  - 0x00
[    2.817475] DSI84-I2C: read 0x3b  - 0x00
jht_8mq:/ #

//-15.6 inch, For 1366 x 768
/*Set the registers on driver*/

/* Soft reset and disable PLL */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_SOFT_RESET, 0x01);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_PLL_EN, 0x00);

/* four DSI lanes with single channel*/
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_CFG, 0x20);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_DSI_EQ, 0x00);

/* set DSI clock range */

i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_DSI_CLK_RNG, 0x2e);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_DSI_CLK_RNG, 0x00);
	
/* set LVDS for single channel, 24 bit mode, HS/VS low, DE high */	
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_LVDS_MODE, 0x78);	

/* x resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_LO, 0x56);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_LINE_LEN_HI, 0x05);

/* x resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_LINE_LEN_HI, 0x00);

/* y resolution high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_LINES_HI, 0x03);

/* y resolution high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_LINES_HI, 0x00);

/* SYNC delay high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_LO, 0x21);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHA_SYNC_DELAY_HI, 0x00);

/* SYNC delay high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, \
		DSI84_CHB_SYNC_DELAY_HI, 0x00);

/* HSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HSYNC_WIDTH_HI, 0x00);

/* HSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VSYNC_WIDTH_HI, 0x00);

/* VSYNC width high/low for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_LO, 0x00);
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VSYNC_WIDTH_HI, 0x00);

/* Horizontal BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_BACKPORCH, 0xC8);

/* Horizontal BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_BACKPORCH, 0x00);

/* Vertical BackPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_BACKPORCH, 0x26);

/* Vertical BackPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_BACKPORCH, 0x00);

/* Horizontal FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_HORZ_FRONTPORCH, 0x00);

/* Horizontal FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_HORZ_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel A */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHA_VERT_FRONTPORCH, 0x00);

/* Vertical FrontPorch for channel B */
i2c_smbus_write_byte_data(dsi84_i2c_client, DSI84_CHB_VERT_FRONTPORCH, 0x00);