******************************************************* Successfully ran Spi polled Example XCLR to low === Initializing === XCLR to high === PS0 === Activate LVDS channels ******************************************************* DisplayPort Pass Through Demonstration (c) 2015 by Xilinx System Configuration: ******************************************************* = XDpRxSs_ReportCoreInfo = DisplayPort RX Subsystem info: DisplayPort Receiver(DPRX):Yes IIC:Yes Audio enabled:No Max supported audio channels:2 Max supported bits per color:8 Supported color format:0 HDCP enabled:No Max supported lane count:4 Max supported link rate:20 Multi-Stream Transport mode:No (SST) Max number of supported streams:1 DP RX Subsystem is running in: SST with streams 1 System capabilities set to: LineRate A, LaneCount 4 **************************r***************************************** In this configuration the RX acts as Master whilethe TX is used to display the video that is received on RX. This mode operates on the clock forwarded by DP159. CPLL is used for RX and TX ******************************************************************* VPHY PLS 0 VPHY PLS 0 RX Link & Lane Capability is set to A, 4 ----------------------------------------------------- -- DisplayPort RX-TX Demo Menu -- ----------------------------------------------------- Select option 1 = Change Lane and Link capabilities 2 = Link, MSA and Error Status 3 = Toggle HPD to ask for Retraining 4 = Restart TX path 5 = Switch TX data to internal pattern generator 6 = Switch TX back to RX video data w = Sink register write r = Sink register read z = Display this menu again x = Return to Main menu ----------------------------------------------------- Please plug in RX cable to initiate training... Dprx_InterruptHandlerPwr Dprx_InterruptHandlerLinkBW Select MAP 0 0000 - 44 50 31 35 39 20 20 20 01 36 1B 18 6C 80 00 0F 0010 - 00 00 00 00 00 00 F1 00 00 00 00 00 00 00 00 00 0020 - 4A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0030 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0040 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0050 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0060 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0070 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0080 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0090 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00A0 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00B0 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Select MAP 1 0000 - E3 02 27 00 80 00 00 00 00 00 00 30 00 02 01 00 0010 - 0F 30 03 00 00 00 00 00 00 00 00 00 00 00 00 00 0020 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0030 - 0F 00 00 F0 01 00 00 00 08 00 08 00 04 06 00 00 0040 - 80 80 80 80 EA 00 00 00 7F 80 FE 3F 01 18 88 88 0050 - 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40 0060 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0070 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0080 - 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0090 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00A0 - 00 02 F6 00 02 00 00 00 00 00 00 00 00 00 00 00 00B0 - F4 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 LOCK_STATUS : 64 TST_INT/Q : 0 BERT counter0[7:0] : 5 BERT counter0[11:8] : 0 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 0 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Dprx_InterruptHandlerTrainingDone Select MAP 0 0000 - 44 50 31 35 39 20 20 20 01 36 3B 18 6C 80 00 0F 0010 - 00 00 00 00 00 80 F1 00 00 00 00 00 00 00 00 00 0020 - 4A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0030 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0040 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0050 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0060 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0070 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0080 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0090 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00A0 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00B0 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Select MAP 1 0000 - E3 02 27 00 80 00 00 00 00 00 00 30 00 02 01 00 0010 - 0F 30 03 00 00 00 00 00 00 00 00 00 00 00 00 00 0020 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0030 - 0F 00 00 F0 01 00 00 00 08 00 08 00 04 06 00 00 0040 - 80 80 80 80 EA 00 00 00 FF 80 FC 3F 03 18 00 00 0050 - 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40 0060 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0070 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0080 - 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0090 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00A0 - 00 02 F6 00 02 00 00 00 00 00 00 00 00 00 00 00 00B0 - F4 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 LOCK_STATUS : 64 TST_INT/Q : 0 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 > Interrupt: Training done !!!(BW: 0xA, Lanes: 0x4, Status: 0x77;0x77). Dprx_InterruptHandlerNoVideo Dprx_InterruptHandlerVideo 20 vblanks 200 vblanks = XDpRxSs_ReportLinkInfo = LINK_BW_SET (0x400) status in DPCD = 0xA LANE_COUNT_SET (0x404) status in DPCD = 0x4 LANE0_1_STATUS (0x043C) in DPCD = 0x77 LANE2_3_STATUS (0x440) in DPCD = 0x77 SYM_ERR_CNT01 (0x448) = 0xFFFFFFFF SYM_ERR_CNT23 (0x44C) = 0xFFFFFFFF PHY_STATUS (0x208) = 0xF000FF = XDpRxSs_ReportMsaInfo = RX MSA registers: Clocks, H Total (0x510) : 3600 Clocks, V Total (0x524) : 1375 HSyncPolarity (0x504) : 0 VSyncPolarity (0x518) : 0 HSync Width (0x508) : 32 VSync Width (0x51C) : 5 Horz Resolution (0x500) : 3200 Vert Resolution (0x514) : 1200 Horz Start (0x50C) : 96 Vert Start (0x520) : 119 Misc0 (0x528) : 0x00000020 Misc1 (0x52C) : 0x00000000 User Pixel Width (0x010) : 4 M Vid (0x530) : 36045 N Vid (0x534) : 32768 M Aud (0x324) : 0 N Aud (0x328) : 0 VB-ID (0x538) : 0 = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 0 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 *** Detected resolution: 3200 x 1200*** Select MAP 0 0000 - 44 50 31 35 39 20 20 20 01 36 3B 18 6C 80 00 0F 0010 - 00 00 00 00 00 80 F1 00 00 00 00 00 00 00 00 00 0020 - 4A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0030 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0040 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0050 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0060 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0070 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0080 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0090 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00A0 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00B0 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Select MAP 1 0000 - E3 02 27 00 80 00 00 00 00 00 00 30 00 02 01 00 0010 - 0F 30 03 00 00 00 00 00 00 00 00 00 00 00 00 00 0020 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0030 - 0F 00 00 F0 01 00 00 00 08 00 08 00 04 06 00 00 0040 - 80 80 80 80 EA 00 00 00 FF 80 FC 3F 03 18 00 00 0050 - 00 00 00 00 00 00 00 00 00 00 00 00 40 40 40 40 0060 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0070 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0080 - 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0090 - 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00A0 - 00 02 F6 00 02 00 00 00 00 00 00 00 00 00 00 00 00B0 - F4 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 vblank_done == 1 Dprx_InterruptHandlerVideo Dprx_InterruptHandlerVideo Dprx_InterruptHandlerVideo *** Detected resolution: 3200 x 1200 @ 60Hz, BPC = 8, Color = 0*** Fifo_data 0 Accumulator is 0, ### Fifo_data -266, +++ Fifo_data -555, +++ Fifo_data -612, +++ Fifo_data -91 Fifo_data 46 Fifo_data 13 Fifo_data -19 Fifo_data -52 Fifo_data -84 Fifo_data -117 Fifo_data -150 Fifo_data -206, +++ Fifo_data -214, +++ Fifo_data -247, +++ Fifo_data -280, +++ Fifo_data -312, +++ Fifo_data -345, +++ Fifo_data -378, +++ Fifo_data -410, +++ Fifo_data -468, +++ Fifo_data 59 Fifo_data 191 Fifo_data 159 Fifo_data 127 Fifo_data 95 Fifo_data 63 Fifo_data 31 Fifo_data -1 Fifo_data -61 Fifo_data -65 Fifo_data -97 Fifo_data -129 Fifo_data -161