#if 1
     write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, SER_RESET_CTL_REG, 0x08); /*disable DSI before setting */
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x01); //Select FPD-Link III Port 0
     write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x5B, 0x05); /*DUAL_CTL1 - select twisted pair cable, force independent 2:2  output mode */
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x04); //Use I2D ID+1 for FPD-Link III Port 1 register access
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x01) ;//Select FPD-Link III Port 0
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x03,0x9A); //Enable I2C_PASSTHROUGH, FPD-Link III Port 0
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x02); //Select FPD-Link III Port 1
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x03,0x9A); //Enable I2C_PASSTHROUGH, FPD-Link III Port 1
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x01); //Select FPD-Link III Port 0
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x40,0x04); //Select DSI Port 0 digital registers//modifed
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x41,0x21); //Select DSI_CONFIG_1 register
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x42,0x60); //Set DSI_VS_POLARITY=DSI_HS_POLARITY=1 //ok
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x02); //Select FPD-Link III Port 1
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x40,0x08); //Select DSI Port 1 digital registers
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x41,0x21) ;//Select DSI_CONFIG_1 register
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x42,0x60) ;//Set DSI_VS_POLARITY=DSI_HS_POLARITY=1
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x01) ;//Select FPD-Link III Port 0   //OK
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x4F,0x8C); //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 0
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x01); //Select FPD-Link III Port 0  //ok
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x40,0x04); //Select DSI Port 0 digital registers
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x41,0x05); //Select DPHY_SKIP_TIMING register
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x42,0x1E); //Write TSKIP_CNT value for 315 MHz DSI clock frequency (1080p, PCLK = 105 MHz) //OK
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x1E,0x02); //Select FPD-Link III Port 1
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x4F,0x8C); //Set DSI_CONTINUOUS_CLOCK, 4 lanes, DSI Port 1 //OK
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x40,0x08); //Select DSI Port 1 digital registers
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x41,0x05); //Select DPHY_SKIP_TIMING register //ok
     write_ds90u941(ti_dev->fd, ti_dev->deser_ctrl,0x42,0x14); //Write TSKIP_CNT value for 225 MHz DSI clock frequency (720p, PCLK = 75 MHz)
     write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x02, 0x01); /*DEVICE_CFG - reverse Lane lines only for port 0*/
    /*finally enable bridge device DSI */
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, SER_RESET_CTL_REG, 0x00);
#endif
#if 1 //1920X720
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x03);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x03);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x07);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x80);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x08);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x07);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x09);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x2d);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x04);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0xB0);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x05);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0xF7);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x06);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x2d);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x0c);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x24);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x0d);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x8);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x0a);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x08);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x0b);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x04);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x66, 0x0e);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x67, 0x0);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x65, 0x07);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x39, 0x02);
    write_ds90u941(ti_dev->fd, ti_dev->chip_ctrl, 0x64, 0x11);
#endif