/******************************************************************************* ** KPIT Technologies Limited ** ** ** ** KPIT Technologies Limited owns all the rights to this work. This work ** ** shall not be copied, reproduced, used, modified or its information ** ** disclosed without the prior written authorization of KPIT Technologies ** ** Limited. ** ** ** ** MODULE : EthTrcv.c ** ** ** ** TARGET : Not Applicable ** ** ** ** PURPOSE : Source File for EthTrcv ** ** ** ** PLATFORM DEPENDANT [yes/no] : no ** ** ** ** TO BE CHANGED BY USER [yes/no]: no ** ** ** *******************************************************************************/ #include #include #define ETH_TRCV_IDX_12 12 void Eb_Intgr_EthTrcvInit_Initialization(const uint8 CtrlIdx) { uint8 EthTrcvIdx; EthTrcvIdx = ETH_TRCV_IDX_12; uint16 RegVal; Eth_ReadMii( CtrlIdx, EthTrcvIdx, 2, &RegVal); //read reg 2 val 0x2000 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 3, &RegVal); //read reg 3 val 0xa231 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 31, 0x8000); //write reg 31 val 0x8000 usleep(10); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read reg 0 val 0x1140 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1140); //write reg 0 val 0x1140 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00FE); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0xe721); //write 254 val 0xe721 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 31, 0x8000); //write reg 31 val 0x8000 usleep(10); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 16, &RegVal); //read reg 16 val 0x5048 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 16, 0x5048); //write reg 16 val 0x5048 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0x1E, 0x202); //write reg 0x1E val 0x0202 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0x1E, &RegVal); //read reg 0x1E val 0x0202 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0032); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 50 val 0x00d1 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00D3); //write reg 50 val 0x00d3 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 50 val 0x00d3 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0086); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00A9); //write reg 134 val 0x00a9 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0170); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 0x170 val 0x0c0f Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0c1f); //write reg 0x170 val 0x0c1f Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0172); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 0x0172 val 0x0000 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0006); //write reg 0x0172 val 0x0006 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 24, 0x5160); //write reg 24 val 0x5160 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x7949 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 15, &RegVal); //read reg 15 val 0x3000 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 4, &RegVal); //read reg 4 val 0x01e1 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 4, 0x0181); //write reg 4 val 0x0181 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 9, &RegVal); //read reg 9 val 0x0300 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 9, 0x0000); //write reg 9 val 0x0000 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read reg 0 val 0x1140 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1140); //write reg 0 val 0x1140 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read reg 0 val 0x1140 Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1340); //write reg 0 val 0x1340 usleep(50); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read reg 0 val 0x1140 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x7949 usleep(80); Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x796d Eth_ReadMii( CtrlIdx, EthTrcvIdx, 4, &RegVal); //read reg 4 val 0x0181 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 5, &RegVal); //read reg 5 val 0xcde1 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 9, &RegVal); //read reg 9 val 0x0000 Eth_ReadMii( CtrlIdx, EthTrcvIdx, 10, &RegVal); //reg 10 val 0x0800 } void Eb_Intgr_EthTrcvWaitLinkUp(const uint8 CtrlIdx) { uint16 RegVal; uint8 EthTrcvIdx; EthTrcvIdx = ETH_TRCV_IDX_12; do { /** PHY register might take some time to update internal registers */ Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0x11U, &RegVal); } while( (0x0400U & RegVal) == 0U); } void Eb_Intgr_EthTrcvInitRGMII(uint8 CtrlIdx) { Eb_Intgr_EthTrcvInit_Initialization(CtrlIdx); Eb_Intgr_EthTrcvWaitLinkUp( CtrlIdx); }