>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>> Register readouts
>>
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Reg address 00 value = 3100 
Reg address 01 value = 7849 
Reg address 02 value = 2000 
Reg address 03 value = A130 
Reg address 04 value = 1E1 
Reg address 05 value = 0 
Reg address 06 value = 4 
Reg address 07 value = 2001 
Reg address 08 value = 0 
Reg address 09 value = 0 
Reg address 0A value = 100 
Reg address 0B value = 0 
Reg address 0C value = 0 
Reg address 0D value = 0 
Reg address 0E value = 0 
Reg address 0F value = 0 
Reg address 10 value = 2 
Reg address 11 value = 108 
Reg address 12 value = 0 
Reg address 13 value = 800 
Reg address 14 value = 0 
Reg address 15 value = 0 
Reg address 16 value = 100 
Reg address 17 value = 41 
Reg address 18 value = 400 
Reg address 19 value = C001 
Reg address 1A value = 0 
Reg address 1B value = 7D 
Reg address 1C value = 5EE 
Reg address 1D value = 0 
Reg address 1E value = 2 
Reg address 1F value = 0 
Reg address 25 value = 0 
Reg address 467 value = FFFF 
Reg address 468 value = FFFF 
Reg address 4D1 value = FFFF 


>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>>> STRAPPING REPORT
>>>
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
REG 0x00: 3100

Bit 13 Speed Selection RW, Strap 1 (CORRECT)
Speed Select:
1 = 100 Mbps
0 = 10 Mbps
When Auto-Negotiation is disabled (bit[12] = 0 in Register 0x0000),
writing to this bit allows the port speed to be selected.

bit 12 Auto-Negotiation Enable RW, Strap 1 (Correct)
Auto-Negotiation Enable:
1 = Enable Auto-Negotiation
0 = Disable Auto-Negotiation
If Auto-Negotiation is disabled, bit[8] and bit[13] of this register
determine the port speed and duplex mode


8 Duplex Mode RW, Strap 1 (CORRECT)
Duplex Mode:
1 = Full-Duplex
0 = Half-Duplex
When Auto-Negotiation is disabled, writing to this bit allows the port
Duplex capability to be selected.

REG 0x0A : 100

14 100Base-FX Enable RW, Strap 0 (CORRECT)
100Base-FX Enable:
1 = 100Base-FX mode enabled
0 = 100Base-FX mode disabled

REG 0x17 : 49

BIT 9 RGMII Mode RW, Strap 0 (CORRECT)
RGMII Mode Enable:
1 = Enable RGMII mode of operation
0 = Mode determined by bit[5]5 
->>>>>Bit 5 RMII Mode RW 0
RMII Mode Enable:
1 = Enable RMII mode of operation
0 = Enable MII mode of operation (MII Mode)

BIT 7 RMII Clock Select RW, Strap 0 (CORRECT)
RMII Reference Clock Select:
Strap XI_50 determines the clock reference requirement.
1 = 50-MHz clock reference, CMOS-level oscillator
0 = 25-MHz clock reference, crystal or CMOS-level oscillato


REG 0x18 : 400
TI says polarity WRONG!!!!! (Default Correct)

BIT 7 LED_0 Polarity RW, Strap 0
LED_0 Link Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting
LED_0 polarity defined by strapping value of this pin. This register
allows for override of this strap value.

REG 0x19 : CC01

BIT 15 Auto MDI/X Enable RW, Strap 0 (NOT CORRECT == 1_
Auto-MDIX Enable:
1 = Enable Auto-Negotiation Auto-MDIX capability
0 = Disable Auto-Negotiation Auto-MDIX capability

BIT 5 LED Configuration RW, Strap 1 (NOT CORRECT == 0)
Configuration LED_CFG LED_0
1 1
ON for LINK
OFF for no LINK
2 0
ON for LINK
BLINK for TX/RX Activity

BIT 0:4 
4:0 PHY Address RO, Strap 0000 1 (CORRECT, Address is 1)
PHY Address:
Strapping configuration for PHY Address

REG 0x25 : 45E1

Bit 9 MLED Polarity Swap RW Strap Bit 9: 0) NOT SURE
MLED Polarity Swap: 
The polarity of MLED depends on the routing configuration and the
strap on COL pin. If the pin strap is Pull-Up then polarity is active low.
If the pin strap is Pull-Down then polarity is active high.

REG" 0x0467 : FFFF (DOES NOT MATCH - SEE Data sheet)

Table 83. 0x0467 Strap Latch-In Register #1 (SOR1) (continued)
BIT NAME TYPE DEFAULT FUNCTION
9:8 RX_ER Strap Mode RO, Strap 11 RX_ER Strap Mode:
Use same reference as defined by bits[15:14] in this register.
7:6 CRS Strap Mode RO, Strap 11 CRS Strap Mode:
Use same reference as defined by bits[15:14] in this register.
5:4 RX_DV Strap Mode RO, Strap 00 RX_DV Strap Mode:
Use same reference as defined by bits[15:14] in this register.
3:2 Reserved RO 00 Reserved
1:0 LED_0 Strap Mode RO, Strap 11
LED_0 Strap Mode:
00 = Mode 1
01 = Reserved
10 = Reserved
11 = Mode 4
Please refer to the strap section in the datasheet for information
regarding PHY configuration.
Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap
Mode and do not reflect the same bit sequence that is defined in the
strap section of the datasheet.

REG: 0x468 : FFFF  (NOT CORRECT)
3:2 RX_D3 Strap Mode RO, Strap 00 RX_D3 Strap Mode:
Use same reference as defined by bits[15:14] in register 0x0467.
1:0 RX_D2 Strap Mode RO, Strap 00 RX_D2 Strap Mode:
Use same reference as defined by bits[15:14] in register 0x0467

REG: 4D1 : FFFF (Not CORRECT)

0 EEE Capabilities Enable RW, Strap 0
EEE Capabilities Enable:
1 = PHY supports EEE capabilities
0 = PHY does not support EEE
When enabled, Auto-Negotiation will negotiate to EEE as defined by
register 0x003C and register 0x003D in MMD7.
When disabled, register 0x0014 in MMD3, register 0x003C and
register 0x003D in MMD7 are ignored.