25G Retimer TESTmemo ---------------------------------------- Reg_0x02[7:0] = CDR_STATUS added ---------------------------------------- Execution script // test 01 - 03 // test_01-03_reg_0x02_20230224.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_xx2.sh // test 01V - 03V eq_vga11 // test_01v-03v_reg_0x02_20230224.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_eq_vga_set.sh ./25g_retimer_test_xx2.sh ---------------------------------------- CDR Bypass, Pre-LOCK = Raw Data, Post = Retimed Data Link Status is on CPU side --> Link NG Yes ---------------------------------------- Execution script // test 01 - 03 // test_01-03_cdr_bypass_pre_20230224.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_cdr_bypass_pre.sh ./25g_retimer_test_xx3.sh // test 01V - 03V eq_vga11 // test_01v-03v_cdr_bypass_pre_20230224.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_cdr_bypass_pre.sh ./25g_retimer_test_eq_vga_set.sh ./25g_retimer_test_xx3.sh ---------------------------------------- CDR Bypass, Pre-LOCK = Raw Data, Post-LOCK = Raw Data Link status is on CPU side --> Link NG Gone ---------------------------------------- Execution script // test 01 - 03 // test_01-03_cdr_bypass_pre_post_20230224.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_cdr_bypass_pre_post.sh ./25g_retimer_test_xx3.sh // test 01V - 03V eq_vga11 // test_01v-03v_cdr_bypass_pre_post_20230224.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_cdr_bypass_pre_post.sh ./25g_retimer_test_eq_vga_set.sh ./25g_retimer_test_xx3.sh ---------------------------------------- Changed RS-FEC setting to no FEC setting No changed ---------------------------------------- Execution script // test 01 - 03 // test_01-03_reg_0x02_fec_none_20230302.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_xx2.sh // test 01V - 03V eq_vga11 // test_01v-03v_reg_0x02_fec_none_20230302.txt ./25g_retimer_setup_reset.sh ./25g_retimer_test_eq_vga_set.sh ./25g_retimer_test_xx2.sh