// DP83TG720 PHY address is 0x08

begin

// Set PMA_PMD_CONTROL Register (Offset = 1834h) [Reset = 8001h]
// Requires indirect addressing: (sec 6.4.9.2 of datasheet)
// https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1608641/dp83tg720evm-mc-dp83tg720-register-access-for-test-modes
000D 0001
000E 0834
000D 4001
000E 4000

// Read back
000D 0001
000E 0834
000D 4001
000E

end