PMIC: LD03 (BANK 45,46) set to 1.800V CLK: Clk synthesizer-1 configured Zynq MP First Stage Boot Loader Release 2025.2 Apr 7 2026 - 11:50:20 PMU-FW is not running, certain applications may not be supported. ------------------------------------------ --- HDMI 2.1 SS + HdmiPhy VRR Example v1.0 --- --- (c) 2019 by Xilinx, Inc. --- ------------------------------------------ Build Apr 7 2026 - 11:50:24 ------------------------------------------ Initializing platform. Initializing IIC and clock sources. Initializing Interrupt controller. Interrupt Controller setup successful. Initializing HDMI Video Transmitter. Debug: Entering InitController Debug: Calling XV_Tx_Hdmi_Initialize (SDT) Debug: HdmiTxSsBaseAddr = 0x80020000 Debug: VPhyBaseAddr = 0x80010000 TX: FRL Base: 0x80020180 Initializing Video Phy with Video Transmitter Debug: XV_Tx_Hdmi_Initialize returned SUCCESS HDMI Video Transmitter system setup successful. Initializing HDMI Video Receiver. Debug: Entering XV_Rx_InitController HDMI 2.1 VRR EDID is Initialized !! Debug: Calling XV_Rx_Hdmi_Initialize (SDT) Debug: HdmiRxSsBaseAddr = 0x80050000 RX: FRL Base: 0x80050180 Debug: VPhyBaseAddr = 0x80040000 Initializing Video Phy with Video Receiver Debug: XV_Rx_Hdmi_Initialize returned SUCCESS Debug: XV_Rx_InitController complete HDMI Video Receiver system setup successful. Initializing Example design controller. Initializing TPG. XPAR_V_TPG_SS_0_AXI_GPIO_BASEADDR = 0x80060000 XPAR_V_TPG_SS_0_V_TPG_BASEADDR = 0x80090000 TxRdy GPIO initialized at 0x80000000 Target GPIO BaseAddress: 0x80000000 GPIO TxRdy value after write: 0 TPG and connected GPIO successfully initialized. getting inside . Initializing Frame Buffers. FBWr BaseAddr = 0x80070000 FBRd BaseAddr = 0x80080000 Video Frame Buffer Read Initialization Complete Video Frame Buffer Write Initialization Complete Video Frame Buffer and GPIO to reset the Video Frame Buffer successfully initialized FB Init SUCCESS Status = 0! --------------------------------- --------------------- --- MAIN MENU --- --------------------- i - Info => Shows information about the HDMI RX stream, HDMI TX stream, GT transceivers and PLL settings. l - Detailed Info => Additional/Detail Info of the system c - Change Mode => Change the mode of the application between independent and non-independent modes. r - Resolution => Change the video resolution of the colorbar. f - Frame rate => Change the frame rate of the colorbar. d - Color depth => Change the color depth of the colorbar. s - Color space => Change the color space of the colorbar. q - View 4K Quad Video => Select to display a part 4K Video on TX (TMDS) when RX (FRL) receives 8K Video p - Toggle HPD => Toggles the HPD of HDMI RX. z - GT & HDMI TX/RX log => Shows log information for GT & HDMI TX/RX. e - Edid => Display and set edid. v - Video => Video pattern options. x - Debug Tools => Goto Debug menu. y - HDMI PHY Debug Menu o - OnSemi NB7NQ621M/ TI TMDS1204 Debug Forcing Release of IP Resets via AXI GPIO... Reset lines driven High. TPG=1, FB=3. ======================================== Initialization Verification Report ======================================== --- GPIO Channel 1 (TPG Reset) --- Raw Register Value = 0x00000001 Bit 0 (TPG Reset) = 1 --> TPG is OUT OF RESET (Active) --- GPIO Channel 2 (Frame Buffer Reset) --- Raw Register Value = 0x00000003 Bit 0 (FB Write Reset) = 1 --> Frame Buffer Write is OUT OF RESET (Active) Bit 1 (FB Read Reset) = 1 --> Frame Buffer Read is OUT OF RESET (Active) Combined FB Reset Value = 0x3 (Expected 0x3 = Both Active) --- GPIO Initialization Status --- GPIO IsReady = 0x11111111 --> INITIALIZED OK GPIO BaseAddress = 0x80060000 --- TPG Initialization Status --- TPG IsReady = 0x11111111 --> INITIALIZED OK TPG BaseAddress = 0x80090000 --- Frame Buffer Write Initialization Status --- FBWr IsReady = 0x11111111 --> INITIALIZED OK FBWr BaseAddress = 0x80070000 FBWr AXI Data Width = 512 bits --- Frame Buffer Read Initialization Status --- FBRd IsReady = 0x11111111 --> INITIALIZED OK FBRd BaseAddress = 0x80080000 FBRd AXI Data Width = 512 bits --- Video Buffer Addresses --- VidBuff[0] Luma BaseAddr = 0x30000000 VidBuff[0] Chroma BaseAddr = 0x35000000 VidBuff[1] Luma BaseAddr = 0x40000000 VidBuff[1] Chroma BaseAddr = 0x45000000 VidBuff[2] Luma BaseAddr = 0x50000000 VidBuff[2] Chroma BaseAddr = 0x55000000 VidBuff[3] Luma BaseAddr = 0x60000000 VidBuff[3] Chroma BaseAddr = 0x65000000 VidBuff[4] Luma BaseAddr = 0x70000000 VidBuff[4] Chroma BaseAddr = 0x75000000 ======================================== SUMMARY ======================================== GPIO : OK TPG : OK FB Write : OK FB Read : OK TPG Reset : Released (Active) FB Write Reset: Released (Active) FB Read Reset: Released (Active) ======================================== --------------------- --- MAIN MENU --- --------------------- i - Info => Shows information about the HDMI RX stream, HDMI TX stream, GT transceivers and PLL settings. l - Detailed Info => Additional/Detail Info of the system c - Change Mode => Change the mode of the application between independent and non-independent modes. r - Resolution => Change the video resolution of the colorbar. f - Frame rate => Change the frame rate of the colorbar. d - Color depth => Change the color depth of the colorbar. s - Color space => Change the color space of the colorbar. q - View 4K Quad Video => Select to display a part 4K Video on TX (TMDS) when RX (FRL) receives 8K Video p - Toggle HPD => Toggles the HPD of HDMI RX. z - GT & HDMI TX/RX log => Shows log information for GT & HDMI TX/RX. e - Edid => Display and set edid. v - Video => Video pattern options. x - Debug Tools => Goto Debug menu. y - HDMI PHY Debug Menu o - OnSemi NB7NQ621M/ TI TMDS1204 Debug VERBOSITY is disabled : 0 VERBOSITY is disabled : 0 VERBOSITY is disabled : 0 Set TX stream to HDMI FRL, sink is HDMI EDID Parsing Pass XV_Tx_HdmiTrigCb_SetupTxFrlRefClk VPHY Error: See log for details Warning: Connected Sink's EDID indicates Deep Color of 16 BpC Not Supported --------------------- --- EDID MENU --- --------------------- 1 - Display the EDID of the connected sink device. 2 - Clone the EDID of the connected sink to HDMI Rx EDID. 3 - Load default EDID to HDMI Rx. --------------------- Load HDMI Rx EDID : --------------------- 10 - TMDS. 12 - RX FRL 4 Lanes 10G. 13 - RX FRL 4 Lanes 8G. 14 - RX FRL 4 Lanes 6G. 15 - RX FRL 3 Lanes 6G. 16 - RX FRL 3 Lanes 3G. 99 - Exit Enter Selection -> 1 MFG name : DEL Number of Segment : 2 Raw data ---------------------------------------------------- ---- Segment 0 ---- ---------------------------------------------------- 00 : 00 FF FF FF FF FF FF 00 10 AC 47 43 4C 44 4A 42 10 : 2A 23 01 03 80 3C 22 78 EA 2B 15 AF 4F 45 A7 25 20 : 0F 50 54 A5 4B 00 71 4F 81 00 81 80 A9 40 B3 00 30 : D1 C0 D1 00 A9 C0 08 E8 00 30 F2 70 5A 80 B0 58 40 : 8A 00 55 50 21 00 00 1E 00 00 00 FF 00 31 42 54 50 : 46 47 38 34 0A 20 20 20 20 20 00 00 00 FC 00 41 60 : 57 32 37 32 35 51 46 0A 20 20 20 20 00 00 00 FD 70 : 00 30 A5 1E FF 3C 00 0A 20 20 20 20 20 20 01 C2 80 : 02 03 50 B1 E2 78 02 4F 61 76 60 3F 10 1F 5F 5E 90 : 5D 22 04 13 12 03 01 6D 03 0C 00 10 00 38 44 20 A0 : 00 60 01 02 03 6D D8 5D C4 01 78 88 6B 02 30 A5 B0 : C3 64 14 E3 05 C3 01 E6 06 05 01 77 60 1B EB 01 C0 : 46 D0 00 4C 82 6D 8B 48 6F 8F E2 00 D5 E2 0F 07 D0 : 6F C2 00 A0 A0 A0 55 50 30 20 35 00 55 50 21 00 E0 : 00 1A 56 5E 00 A0 A0 A0 29 50 30 20 35 00 55 50 F0 : 21 00 00 1A 00 00 00 00 00 00 00 00 00 00 00 F5 ---- Segment 1 ---- ---------------------------------------------------- 00 : 70 12 79 03 00 03 01 50 9A 08 02 04 FF 0E 9F 00 10 : 2F 80 1F 00 6F 08 99 00 02 00 04 00 BB 5A 02 04 20 : FF 0E 9F 00 2F 80 1F 00 6F 08 B1 00 02 00 04 00 30 : 3D 11 01 04 FF 09 9F 00 2F 80 1F 00 9F 05 76 00 40 : 02 00 04 00 A3 9C 00 04 7F 07 9F 00 2F 80 1F 00 50 : 37 04 58 00 02 00 04 00 00 00 00 00 00 00 00 00 60 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 6C 90 80 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 D0 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 E0 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 VERBOSITY is disabled : 0 VERBOSITY is disabled : 0 VERBOSITY is disabled : 0 HDMI Forum EDID extension override Data Block VERBOSITY is disabled : 1 VERBOSITY is disabled : 1 VERBOSITY is disabled : 1 Enter Selection -> 99 Returning to main menu. --------------------- --- DEBUG MENU --- ---------------------- Force TX to perform : 1 - TX TMDS. 3 - TX FRL 4 Lanes 10G. 4 - TX FRL 4 Lanes 8G. 5 - TX FRL 4 Lanes 6G. 6 - TX FRL 3 Lanes 6G. 7 - TX FRL 3 Lanes 3G. 10 - RX Request Rate Drop. 11 - RX sets FltNoTimeout. 12 - RX clears FltNoTimeout. 13 - RX requests for FRL LT (during LTS:P). 14 - RX PHY Reset. 20 - Register Dump (Debug). 21 - SCDC Register Dump (Debug). 99 - Exit Enter Selection -> 1 Enter Selection -> Pass-through Mode - RX : 0, Tx : 1 TMDS Clock:148500000 XV_Tx_VideoSetupAndStart Success VERBOSITY is disabled : 0 VERBOSITY is disabled : 0 VERBOSITY is disabled : 0 Set TX stream to HDMI FRL, sink is HDMI EDID Parsing Pass Status: 1, DdcBuf: 4 SCDC Wrong Version on Connected Sink! Pass-through Mode - RX : 0, Tx : Tx stream is up in colorbar -------- Colorbar : Color Format: RGB Color Depth: 8 Pixels Per Clock: 8 Mode: Progressive DSC Status: Uncompressed Frame Rate: 60Hz Resolution: 1920x1080@60Hz Pixel Clock: 148500 kHz TX Mode: TMDS -------- Hdmiphy1HdmiTxReadyCallback,189, 1 TMDS Clock:148500000 XV_Tx_VideoSetupAndStart Success xInvalid input. Valid entry is only digits 0-9. Try again Enter Selection -> 4 Enter Selection -> XV_Tx_HdmiTrigCb_SetupTxFrlRefClk Hdmiphy1HdmiTxReadyCallback,189, Pass-through Mode - RX : 0, Tx : 1 TMDS Clock:148500000 Tx stream is up in colorbar -------- Colorbar : Color Format: RGB Color Depth: 8 Pixels Per Clock: 8 Mode: Progressive DSC Status: Uncompressed Frame Rate: 60Hz Resolution: 1920x1080@60Hz Pixel Clock: 148500 kHz TX FRL Rate: 4 lanes @ 8 Gbps -------- XV_Tx_VideoSetupAndStart Success HDMIPHY log ------ GT init start GT init done TX TMDS Reconfig TX TMDS Reconfig Error! TX: Line rates > 8.0 Gbps are not supported by -1/-1LV devices TX frequency event TX frequency event TX frequency event TX timer event QPLL reconfig done GT TX reconfig start GT TX reconfig done TX TMDS Reconfig TX frequency event TX TMDS Reconfig TX TMDS Reconfig TX frequency event TX timer event TX MMCM reconfig done QPLL reconfig done GT TX reconfig start GT TX reconfig done TX MMCM lock QPLL lock TX reset done TX alignment done TX FRL Reconfig TX frequency event QPLL lost lock TX frequency event TX MMCM reconfig done QPLL reconfig done GT TX reconfig start GT TX reconfig done TX MMCM lock QPLL lock TX reset done TX alignment done HDMIPHY log ------ GT init start GT init done TX frequency event RX frequency event RX timer event RX DRU disable CPLL reconfig done GT RX reconfig start GT RX reconfig done CPLL lock RX reset done RX TMDS Reconfig HDMI TX log ------ Initializing HDMI TX core.... Initializing VTC core.... Reset HDMI TX Subsystem.... Start HDMI TX Subsystem.... Cable is connected.... FRL Start Training (MaxFrlRate: 6) FRL Config FRL LTS:2 (FRL_Rate: 10 FFE_Levels: 0) Stream is Down TMDS Start Set Stream Cable is disconnected.... Cable is connected.... FRL Start Training (MaxFrlRate: 6) Stream is Down TMDS Start Audio Unmuted Set Audio Channels (2) Stream Start Stream is Up Set Stream VID Bridge Locked FRL Start Training (MaxFrlRate: 4) FRL Config FRL LTS:2 (FRL_Rate: 8 FFE_Levels: 0) VID Bridge Unlocked Stream is Down FRL LTS:3 (LTP: 0x5) FRL LTS:3 (LTP: 0x6) FRL LTS:3 (LTP: 0x7) FRL LTS:3 (LTP: 0x8) FRL LTS:3 (LT Pass) FRL LT Pass FRL LTS:P (LT passed) Set Stream Stream is Down Audio Unmuted Set Audio Channels (2) Stream Start Stream is Up VID Bridge Locked HDMI RX log ------ Initializing HDMI RX core.... Reset HDMI RX Subsystem.... TMDS reference clock change Stream Init Start HDMI RX Subsystem.... Stream Start