/******    TL16C754C Register Initialization Test Program    *****/
/*                                 */
/* Texas Instruments, Inc., 02-20-06                   */
/* Use 754C device on the 754CPM evaluation board.                    */
/* This program assumes a device is in socket, and address            */
/*   decode is set to x300-ChanA, x308-ChanB, x310-ChanC, x318-ChanD  */
/* This pgm sets up basic UART functionality with divisor = 11,       */
/*   all interrupts enabled, fifos enabled, and flow control disabled */
/*    							              */

#include <dos.h>
#include <stdio.h>
#include <conio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>

/* Comm Port 1 or A -- UART register set definition */
#define RBR_UART1      0x300  /*Receiver Buffer Register of chA */
#define THR_UART1      0x300  /*Transmitter Holding Register of chA */
#define IER_UART1      0x301  /*Interrupt Enable Register of chA */
#define IIR_UART1      0x302  /*Interrupt Identify Register of chA */
#define FCR_UART1      0x302  /*FIFO Control Register of chA */
#define LCR_UART1      0x303  /*Line Control Register of chA */
#define MCR_UART1      0x304  /*Modem Control Register of chA */
#define LSR_UART1      0x305  /*Line Status Register of chA */
#define MSR_UART1      0x306  /*Modem Status Register of chA*/
#define SPR_UART1      0x307  /*Scratch Pad Register of chA */
#define DLL_UART1      0x300  /*Divisor Latch LSB of chA */
#define DLM_UART1      0x301  /*Divisor Latch MSB of chA */
/* End Comm Port definition */

/* Comm Port 2 or B -- UART register set definition */
#define RBR_UART2      0x308  /*Receiver Buffer Register of chB */
#define THR_UART2      0x308  /*Transmitter Holding Register of chB */
#define IER_UART2      0x309  /*Interrupt Enable Register of chB */
#define IIR_UART2      0x30A  /*Interrupt Identify Register of chB */
#define FCR_UART2      0x30A  /*FIFO Control Register of chB */
#define LCR_UART2      0x30B  /*Line Control Register of chB */
#define MCR_UART2      0x30C  /*Modem Control Register of chB */
#define LSR_UART2      0x30D  /*Line Status Register of chB */
#define MSR_UART2      0x30E  /*Modem Status Register of chB*/
#define SPR_UART2      0x30F  /*Scratch Pad Register of chB */
#define DLL_UART2      0x308  /*Divisor Latch LSB of chB */
#define DLM_UART2      0x309  /*Divisor Latch MSB of chB */
/* End Comm Port definition */

/* Comm Port 3 or C -- UART register set definition */
#define RBR_UART3      0x310  /*Receiver Buffer Register of chA */
#define THR_UART3      0x310  /*Transmitter Holding Register of chA */
#define IER_UART3      0x311  /*Interrupt Enable Register of chA */
#define IIR_UART3      0x312  /*Interrupt Identify Register of chA */
#define FCR_UART3      0x312  /*FIFO Control Register of chA */
#define LCR_UART3      0x313  /*Line Control Register of chA */
#define MCR_UART3      0x314  /*Modem Control Register of chA */
#define LSR_UART3      0x315  /*Line Status Register of chA */
#define MSR_UART3      0x316  /*Modem Status Register of chA*/
#define SPR_UART3      0x317  /*Scratch Pad Register of chA */
#define DLL_UART3      0x310  /*Divisor Latch LSB of chA */
#define DLM_UART3      0x311  /*Divisor Latch MSB of chA */
/* End Comm Port definition */

/* Comm Port 4 or D -- UART register set definition */
#define RBR_UART4      0x318  /*Receiver Buffer Register of chB */
#define THR_UART4      0x318  /*Transmitter Holding Register of chB */
#define IER_UART4      0x319  /*Interrupt Enable Register of chB */
#define IIR_UART4      0x31A  /*Interrupt Identify Register of chB */
#define FCR_UART4      0x31A  /*FIFO Control Register of chB */
#define LCR_UART4      0x31B  /*Line Control Register of chB */
#define MCR_UART4      0x31C  /*Modem Control Register of chB */
#define LSR_UART4      0x31D  /*Line Status Register of chB */
#define MSR_UART4      0x31E  /*Modem Status Register of chB*/
#define SPR_UART4      0x31F  /*Scratch Pad Register of chB */
#define DLL_UART4      0x318  /*Divisor Latch LSB of chB */
#define DLM_UART4      0x319  /*Divisor Latch MSB of chB */
/* End Comm Port definition */

// useful status defines for interrupt checking
#define recv_lin_stat    0xC6   /* FIFO enabled, receiver line status error*/
#define recv_data_avail  0xC4   /* Trigger lever reached */
#define char_time_out    0xCC   /* Character time_out */
#define xmt_thr_empty    0xC2   /* Transmitter Holding Register Empty */


main(
	

	// setup ports (same ol' stuff)
	/* Port 1 - Channel A */
	outportb(LCR_UART1, 0x80);     /* Enable divisor access */
	outportb(DLL_UART1, 0x0b;      /* set divisor           */
	outportb(DLM_UART1, 0x00);
	outportb(LCR_UART1, 0x03);     /* Set 8,N,1 data        */
	outportb(FCR_UART1, 0xC7);     /* Enable and clear FIFOs, Rcv thresh=60  */     
	outportb(IER_UART1, 0x0F);     /* Enable all interrupts */
	outportb(MCR_UART1, 0x00);     /* Disable flow control   */
	
	 /* Port 2 - Channel B */
	outportb(LCR_UART2, 0x80);     /* Enable divisor access */
	outportb(DLL_UART2, 0x0b);     /* set divisor           */
	outportb(DLM_UART2, 0x00);
	outportb(LCR_UART2, 0x03);     /* Set 8,N,1 data */
	outportb(FCR_UART2, 0xC7);     /* Enable and clear FIFOs, Rcv thresh=60  */ 
	outportb(IER_UART2, 0x0F);     /* Enable all ints */
	outportb(MCR_UART2, 0x00);     /* Disable flow control   */

	/* Port 3 - Channel C */
	outportb(LCR_UART3, 0x80);     /* Enable divisor access */
	outportb(DLL_UART3, 0x0b;      /* set divisor           */
	outportb(DLM_UART3, 0x00);
	outportb(LCR_UART3, 0x03);     /* Set 8,N,1 data        */
	outportb(FCR_UART3, 0xC7);     /* Enable and clear FIFOs, Rcv thresh=60  */     
	outportb(IER_UART3, 0x0F);     /* Enable all interrupts */
	outportb(MCR_UART3, 0x00);     /* Disable flow control   */
	
	 /* Port 4 - Channel D */
	outportb(LCR_UART4, 0x80);     /* Enable divisor access */
	outportb(DLL_UART4, 0x0b);     /* set divisor           */
	outportb(DLM_UART4, 0x00);
	outportb(LCR_UART4, 0x03);     /* Set 8,N,1 data */
	outportb(FCR_UART4, 0xC7);     /* Enable and clear FIFOs, Rcv thresh=60  */ 
	outportb(IER_UART4, 0x0F);     /* Enable all ints */
	outportb(MCR_UART4, 0x00);     /* Disable flow control   */
	

			
}
/* end of main */