******************************************************* Successfully ran Spi polled Example XCLR to low === Initializing === XCLR to high === PS0 === ******************************************************* DisplayPort Pass Through Demonstration (c) 2015 by Xilinx System Configuration: ******************************************************* = XDpRxSs_ReportCoreInfo = DisplayPort RX Subsystem info: DisplayPort Receiver(DPRX):Yes IIC:Yes Audio enabled:No Max supported audio channels:2 Max supported bits per color:8 Supported color format:0 HDCP enabled:No Max supported lane count:4 Max supported link rate:20 Multi-Stream Transport mode:No (SST) Max number of supported streams:1 DP RX Subsystem is running in: SST with streams 1 System capabilities set to: LineRate A, LaneCount 4 **************************r***************************************** In this configuration the RX acts as Master whilethe TX is used to display the video that is received on RX. This mode operates on the clock forwarded by DP159. CPLL is used for RX and TX ******************************************************************* VPHY PLS 0 VPHY PLS 0 RX Link & Lane Capability is set to A, 4 ----------------------------------------------------- -- DisplayPort RX-TX Demo Menu -- ----------------------------------------------------- Select option 1 = Change Lane and Link capabilities 2 = Link, MSA and Error Status 3 = Toggle HPD to ask for Retraining 4 = Restart TX path 5 = Switch TX data to internal pattern generator 6 = Switch TX back to RX video data w = Sink register write r = Sink register read z = Display this menu again x = Return to Main menu ----------------------------------------------------- Please plug in RX cable to initiate training... VPHY PLS 0 Dprx_InterruptHandlerPwr Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 0 BERT counter0[11:8] : 0 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0xA,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0x6,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0xA,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0x6,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0xA,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0x6,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0xA,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0x6,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0xA,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0x6,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT counter2[7:0] : 0 BERT counter2[11:8] : 0 BERT counter3[7:0] : 0 BERT counter3[11:8] : 0 Dprx_InterruptHandlerPllReset 0 0 Link Rate: 0xA,Lane count: 4 Dprx_InterruptHandlerLinkBW = XDpRxSs_ReportDp159BitErrCount = LOCK_STATUS : 64 TST_INT/Q : 16 BERT counter0[7:0] : 255 BERT counter0[11:8] : 15 BERT counter1[7:0] : 0 BERT counter1[11:8] : 0 BERT c