///*The following code is a stripped down version of a previous project, there
// * may be parts of this code that are unnecessary. This example will create
// * text file and write a few letters. If you have any questions or would like
// * to learn more how to implement this project using more extensive commands
// * please contact me at OCB456@aol.com. Thanks!
// * */
//
//#include <MSP430F5529.h>
//#include "ff.h"
//#include "diskio.h"
//#include "sdmmc.h"
//
//
//
//void main(void)
//{
//    WDTCTL = WDTPW+WDTHOLD;                     // Stop watchdog timer
//    P4SEL |= BIT4+BIT5;             // P3.3,4 = USCI_A0 TXD/RXD
//    UCA1CTL1 |= UCSWRST;            // **Put state machine in reset**
//    UCA1CTL1 |= UCSSEL_2;           // SMCLK
//    UCA1BR0 = 9;                    // 1MHz 115200 (see User's Guide)
//    UCA1BR1 = 0;                    // 1MHz 115200
//    UCA1MCTL |= UCBRS_1 + UCBRF_0;  // Modulation UCBRSx=1, UCBRFx=0
//    UCA1CTL1 &= ~UCSWRST;           // **Initialize USCI state machine**
//    UCA1IE |= UCRXIE;               // Enable USCI_A0 RX interrupt
//
//    __bis_SR_register(GIE);  // interrupts enabled
//    //    char array[] = "birla nesan";
//
//    initCLK();
//    __enable_interrupt();
//
//    fat_init();                                 //mount, set directory to read from, assign file
//
//    unsigned int bytesWritten;
//    int i;
//    char a;
//
//
//    for(i=0; i<100; i++)
//    {
//        f_lseek(&file,i*5 );
//        f_write(&file, "birla", 6, &bytesWritten);
//        __delay_cycles(5000);
//
//    }
//    for(i=0; i<100; i++)
//    {
//        f_lseek(&file,i );
//        f_read(&file,&a,1,&bytesWritten);
//        while (!(UCA1IFG&UCTXIFG));
//        UCA1TXBUF= a; //Write the character at the location specified by the pointer and increment pointer
//
//
//    }
//
//    f_close(&file);
//    f_mount(0,0);
//
//
//    while(1);
//}
























#include <MSP430F5529.h>
#include "ff.h"
#include "diskio.h"

void initCLK(void);
void SetVcoreUp (unsigned int level);
FRESULT WriteFile(char*, char*, WORD);
void fat_init(void);

FIL file;                                               /* Opened file object */
FATFS fatfs;                                            /* File system object */
DIRS dir;                                               /* Directory object   */
DIRS dir2;
FRESULT errCode;                                        /* Error code object  */
FRESULT res;                                            /* Result object      */
UINT bytesRead;                                         /* Bytes read object  */
UINT read;                                              /* Read bytes object  */


FATFS test_for_new; // to check if a new file can be written
FIL test_file;

unsigned char MST_Data,SLV_Data;
BYTE buffer[32];
int result=1;

void main(void){

    WDTCTL = WDTPW+WDTHOLD;                     // Stop watchdog timer

    initCLK();

    __enable_interrupt();



    fat_init();                                 //mount, set directory to read from, assign file
    unsigned int bytesWritten;
    f_write(&file, "abcdefg \r\n", 32, &bytesWritten);
    f_write(&file, "ok", 32, &bytesWritten);
    f_close(&file);
//    f_closedir(&dir);
    f_mount(0,0);


   /* f_mount(0,&test_for_new); // f_mount(0,0);
    //new
    f_open(&test_file, "test_file.txt", FA_CREATE_NEW);
    f_write(&test_file, "Hi Mom", 32, &bytesWritten);
    f_close(&test_file);//new*/
 //   f_closedir(&dir2);
  //  f_mount(0,&test_for_new);
    while(1);
}

void fat_init(void){
    errCode = -1;

    while (errCode != FR_OK){                               //go until f_open returns FR_OK (function successful)
        errCode = f_mount(0, &fatfs);                       //mount drive number 0
        errCode = f_opendir(&dir, "/");                     //root directory

        errCode = f_open(&file, "TESTE.txt", FA_CREATE_ALWAYS | FA_WRITE);
        if(errCode != FR_OK)
            result=0;                                       //used as a debugging flag
    }
}


void initCLK(void){
  volatile unsigned int i;

  // Increase Vcore setting to level3 to support fsystem=25MHz
  // NOTE: Change core voltage one level at a time..
  SetVcoreUp (0x01);
  SetVcoreUp (0x02);
  SetVcoreUp (0x03);

  UCSCTL3 = SELREF_2;                       // Set DCO FLL reference = REFO
  UCSCTL4 |= SELA_2;                        // Set ACLK = REFO

  __bis_SR_register(SCG0);                  // Disable the FLL control loop
  UCSCTL0 = 0x0000;                         // Set lowest possible DCOx, MODx
  UCSCTL1 = DCORSEL_7;                      // Select DCO range 50MHz operation
  UCSCTL2 = FLLD_1 + 762;                   // Set DCO Multiplier for 25MHz
                                            // (N + 1) * FLLRef = Fdco
                                            // (762 + 1) * 32768 = 25MHz
                                            // Set FLL Div = fDCOCLK/2
  __bic_SR_register(SCG0);                  // Enable the FLL control loop

  // Worst-case settling time for the DCO when the DCO range bits have been
  // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
  // UG for optimization.
  // 32 x 32 x 25 MHz / 32,768 Hz ~ 780k MCLK cycles for DCO to settle
  __delay_cycles(782000);

  // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
}

void SetVcoreUp (unsigned int level)
{
  // Open PMM registers for write
  PMMCTL0_H = PMMPW_H;
  // Set SVS/SVM high side new level
  SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
  // Set SVM low side to new level
  SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
  // Wait till SVM is settled
  while ((PMMIFG & SVSMLDLYIFG) == 0);
  // Clear already set flags
  PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
  // Set VCore to new level
  PMMCTL0_L = PMMCOREV0 * level;
  // Wait till new level reached
  if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
  // Set SVS/SVM low side to new level
  SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
  // Lock PMM registers for write access
  PMMCTL0_H = 0x00;
}