// MSP432P401M - ADC14, Sample A1, AVcc Ref and Timer32 Example, One-shot mode in free run // // Description:A single sample is made on A1 with reference to AVcc. // ADC14 internal oscillator times sample (16x) and conversion. // Timer 32 (module 0) is set up in 32-bit, free-run, and periodic mode. // Timer count is loaded with an initial value of 0xFFFFFF. // After perform some function, the timer interrupt triggers // and the ISR is executed. Within the ISR, timer counts down and reaches the 0. // Software sets ADC14_CTL0_SC to start sample and // conversion - ADC14_CTL0 automatically cleared at EOC.It just clears the interrupt flag // and exits back to the main application and enters a while loop. //************************************************************************************************// // SAYALI PATHAK // 3 Feb 2017 (Created) // 8 Feb 2017 (Changes) #include "MSP432P401M.h" #include //Defining variables for inclinometer ADC conversions //Nikhil Bapat 8 Feb 2017 unsigned int i; unsigned int j; unsigned int l=1; //Defining variables for inclinometer voltage to angel conversions // // //Counters for debugging unsigned int m=0; unsigned int n=0; //************************************************************************************* //Main code int main(void) { //Stop watchdog timer WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Configure GPIO //this port pins is used as a UART pin // P1->DIR |= BIT0; //P1->OUT &= ~BIT0; P5->SEL1 |= BIT4; // Configure P5.4 for ADC P5->SEL0 |= BIT4; // UNUSED pin setup P10->DIR &= ~(BIT0 + BIT1 + BIT2 + BIT3); // set P10 as input direction P10->REN |= BIT0 + BIT1 + BIT2 + BIT3; //enable pull-up/pull-down resistors on P10 P10->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3); //Set P10 resistors to pull down P1->DIR &= ~(BIT1 + BIT4 + BIT5 + BIT6 + BIT7); P1->REN |= BIT1 + BIT4 + BIT5 + BIT6 + BIT7; P1->OUT &= ~(BIT1 + BIT4 + BIT5 + BIT6 + BIT7); P2->DIR &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P2->REN |= BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7; P2->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P8->DIR &= BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7; P8->REN |= BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7; P8->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P9->DIR &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5); P9->REN |= BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 ; P9->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5); P6->DIR &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P6->REN |= BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7; P6->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P4->DIR &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P4->REN |= BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7; P4->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P5->DIR &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P5->REN |= BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7; P5->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7); P7->DIR &= ~(BIT0 + BIT1 + BIT2 + BIT3); P7->REN |= BIT0 + BIT1 + BIT2 + BIT3; P7->OUT &= ~(BIT0 + BIT1 + BIT2 + BIT3); /* //SAYALI PATHAK 9 FEB 2017 // Configure DCO to 48MHz, ensure MCLK uses DCO as source CS->KEY = CS_KEY_VAL ; // Unlock CS module for register access CS->CTL0 = 0; // Reset tuning parameters CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM_3; // Select MCLK = DCO, no divider CS->KEY = 0; // Lock CS module from unintended accesses */ //ADC Setup ADC14->CTL0 = ADC14_CTL0_SHT0_2 | ADC14_CTL0_SHP | ADC14_CTL0_ON; // Sampling time, S&H=16, ADC14 on //ADC14->CTL1 = ADC14_CTL1_RES_2; // Use sampling timer, 12-bit conversion results ADC14->CTL1 = ADC14_CTL1_RES_3; // Use sampling timer, 14-bit conversion results ADC14->MCTL[0] |= ADC14_MCTLN_INCH_1; // A1 ADC input select; Vref=AVCC // ADC14->IER0 |= ADC14_IER0_IE0; // Enable ADC conv complete interrupt /* // Timer32 set up in one-shot, free run, 32-bit, no pre-scale TIMER32_1->CONTROL = TIMER32_CONTROL_SIZE | TIMER32_CONTROL_ONESHOT; // Load Timer32 Counter with initial value TIMER32_1->LOAD= 0xFFFFFF; // Enable the Timer32 interrupt in NVIC __enable_irq(); NVIC->ISER[0] = 1 << ((T32_INT1_IRQn) & 31); // Start Timer32 and enable interrupt TIMER32_1->CONTROL |= TIMER32_CONTROL_ENABLE | TIMER32_CONTROL_IE; // Disable sleep on exit from ISR SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; // Enter LPM0 and wait for the timer interrupt to wake-up __sleep(); __no_operation();*/ while (1) { if(l == 1) { // Timer32 set up in periodic ,free run, 32-bit, no pre-scale TIMER32_1->CONTROL = TIMER32_CONTROL_SIZE | TIMER32_CONTROL_ONESHOT; // Load Timer32 Counter with initial value TIMER32_1->LOAD= 0xFFFFFF; // TIMER32_1->LOAD= 0xFFFF; // Enable the Timer32 interrupt in NVIC __enable_irq(); NVIC->ISER[0] = 1 << ((T32_INT1_IRQn) & 31); // Disable sleep on exit from ISR SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; // Start Timer32 and enable interrupt TIMER32_1->CONTROL |= TIMER32_CONTROL_ENABLE | TIMER32_CONTROL_IE; // Enter LPM0 and wait for the timer interrupt to wake-up // __sleep(); // __no_operation(); m++; if (m>50000) { m=0; } l=0; } } } void T32_INT1_IRQHandler(void) { // P1->OUT ^= BIT0; // Toggle P1.0 LED // Start sampling/conversion ADC14->CTL0 |= ADC14_CTL0_ENC | ADC14_CTL0_SC; n++; if (n==50000) { n=0; } TIMER32_1->INTCLR |= BIT0; // Clear Timer32 interrupt flag // Disable the timer and interrupt TIMER32_1->CONTROL &= ~(TIMER32_CONTROL_ENABLE |TIMER32_CONTROL_IE); l= 1; }