#include <msp430.h>

unsigned char RXData = 0;
unsigned char TXData;

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                 // Stop watchdog timer

    __bis_SR_register(SCG0);                // disable FLL
    CSCTL3 |= SELREF__REFOCLK;              // Set REFO as FLL reference source
    CSCTL0 = 0;                             // clear DCO and MOD registers
    CSCTL1 &= ~(DCORSEL_7);                 // Clear DCO frequency select bits first
    CSCTL1 |= DCORSEL_5;                    // Set DCO = 16MHz

    CSCTL2 = FLLD_0 + 426;
    __delay_cycles(3);
    __bic_SR_register(SCG0);                // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // select DCODIV as MCLK and SMCLK source
    CSCTL5 |= DIVS__4;

    P1OUT |= BIT6;
    P1DIR |= BIT6;


    P2SEL0 |= BIT4 | BIT5 | BIT6;             // set 3-SPI pin as second function

    UCA1CTLW0 |= UCSWRST;                     // **Put state machine in reset**
    UCA1CTLW0 |= UCMST|UCSYNC|UCCKPL|UCMSB;   // 3-pin, 8-bit SPI master
                                              // Clock polarity high, MSB
    UCA1CTLW0 |= UCSSEL__SMCLK;                // Select ACLK
    UCA1BR0 = 0x00;                           // BRCLK = ACLK/2
    UCA1BR1 = 0;                              //
    UCA1MCTLW = 0;                            // No modulation
    UCA1CTLW0 &= ~UCSWRST;                    // **Initialize USCI state machine**
//    UCA0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt
    TXData = 0x01;                            // Holds TX data

    PM5CTL0 &= ~LOCKLPM5;                     // Disable the GPIO power-on default high-impedance mode
                                              // to activate previously configured port settings
    while(1)
    {
        UCA1IE |= UCTXIE;                     // Enable TX interrupt
        __bis_SR_register(LPM0_bits | GIE);   // enable global interrupts, enter LPM0
        __no_operation();                     // For debug,Remain in LPM0
        __delay_cycles(2000);                 // Delay before next transmission
        P1OUT &= ~BIT6;
        TXData++;                             // Increment transmit data
    }

//    P1SEL0 |= BIT1 | BIT2 | BIT3;
//
//    UCB0CTLW0 |= UCSWRST;                     // **Put state machine in reset**
//    UCB0CTLW0 |= UCMST|UCSYNC|UCCKPL|UCMSB;   // 3-pin, 8-bit SPI master
//                                              // Clock polarity high, MSB
//    UCB0CTLW0 |= UCSSEL__SMCLK;                // Select ACLK
//    UCB0BR0 = 0x00;                           // BRCLK = ACLK/2
//    UCB0BR1 = 0;                              //
//
//    UCB0CTLW0 &= ~UCSWRST;                    // **Initialize USCI state machine**
//    UCB0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt
//    TXData = 0x01;                            // Holds TX data
//
//    PM5CTL0 &= ~LOCKLPM5;                     // Disable the GPIO power-on default high-impedance mode
//                                              // to activate previously configured port settings
//    while(1)
//    {
//        UCB0IE |= UCTXIE;                     // Enable TX interrupt
//        __bis_SR_register(LPM0_bits | GIE);   // enable global interrupts, enter LPM0
//        __no_operation();                     // For debug,Remain in LPM0
//        __delay_cycles(2000);                 // Delay before next transmission
//        TXData++;                             // Increment transmit data
//    }
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A1_VECTOR))) USCI_A1_ISR (void)
#else
#error Compiler not supported!
#endif
{
    switch(__even_in_range(UCA1IV,USCI_SPI_UCTXIFG))
    {
        case USCI_NONE: break;                // Vector 0 - no interrupt
        case USCI_SPI_UCRXIFG:
              RXData = UCA1RXBUF;
              UCA1IFG &= ~UCRXIFG;
              break;
        case USCI_SPI_UCTXIFG:
              UCA1TXBUF = TXData;             // Transmit characters
              UCA1IE &= ~UCTXIE;
              __bic_SR_register_on_exit(LPM0_bits);// Wake up to setup next TX
              break;
        default: break;
    }
}
//#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
//#pragma vector=USCI_B0_VECTOR
//__interrupt void USCI_B0_ISR(void)
//#elif defined(__GNUC__)
//void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
//#else
//#error Compiler not supported!
//#endif
//{
//    switch(__even_in_range(UCB0IV,USCI_SPI_UCTXIFG))
//    {
//        case USCI_NONE: break;                // Vector 0 - no interrupt
//        case USCI_SPI_UCRXIFG:
//              RXData = UCB0RXBUF;
//              UCB0IFG &= ~UCRXIFG;
//
//              break;
//        case USCI_SPI_UCTXIFG:
//              UCB0TXBUF = TXData;             // Transmit characters
//              UCB0IE &= ~UCTXIE;
//              __bic_SR_register_on_exit(LPM0_bits);// Wake up to setup next TX
//              break;
//        default: break;
//    }
//}