/*
 * dev_init.c
 *
 *  Created on: Mar 7, 2017
 *
 */
#include "MSP432P401M.h"
uint32_t currentPowerState;
void init_32k(void)
{

   // Configure GPIO
    PJ->SEL0 |= BIT0 | BIT1;                // set LFXT pin as second function

    CS->KEY = CS_KEY_VAL ;                  // Unlock CS module for register access

    CS->CTL2 |= CS_CTL2_LFXT_EN;            // LFXT on

    // Loop until XT1, XT2 & DCO fault flag is cleared
    do
    {
       // Clear XT2,XT1,DCO fault flags
       CS->CLRIFG |= CS_CLRIFG_CLR_DCOR_OPNIFG | CS_CLRIFG_CLR_HFXTIFG |
               CS_CLRIFG_CLR_LFXTIFG | CS_CLRIFG_CLR_FCNTLFIFG;
       SYSCTL->NMI_CTLSTAT &= ~ SYSCTL_NMI_CTLSTAT_CS_SRC;

    } while ((SYSCTL->NMI_CTLSTAT | SYSCTL_NMI_CTLSTAT_CS_FLG)
            && (CS->IFG & CS_IFG_LFXTIFG)); // Test oscillator fault flag

    // Select ACLK as LFXTCLK
    CS->CTL1 = CS->CTL1 & ~(CS_CTL1_SELA_MASK | CS_CTL1_DIVA_MASK) | CS_CTL1_SELA_0;


    // Enable LFXT fault interrupt
    CS->IE |= CS_IE_LFXTIE;

    CS->KEY = 0;                            // Lock CS module from unintended accesses

    // Enable global interrupt
    __enable_irq();

    // Enable CS interrupt in NVIC module
    NVIC->ISER[0] = 1 << ((CS_IRQn) & 31);

}
void error(void)
{


 //   while (1);

}

void init_48M(void)
{
        /* Get current power state, if it's not AM0_LDO, error out */
        currentPowerState = PCM->CTL0 & PCM_CTL0_CPM_MASK;
        if (currentPowerState != PCM_CTL0_CPM_0)
            error();
        while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
        PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
        while ((PCM->CTL1 & PCM_CTL1_PMR_BUSY));
        if (PCM->IFG & PCM_IFG_AM_INVALID_TR_IFG)
                error();                            // Error if transition was not successful
        if ((PCM->CTL0 & PCM_CTL0_CPM_MASK) != PCM_CTL0_CPM_1)
                error();                            // Error if device is not in AM1_LDO mode

        /* Step 2: Configure Flash wait-state to 1 for both banks 0 & 1 */
            FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK)) |
                    FLCTL_BANK0_RDCTL_WAIT_1;
            FLCTL->BANK1_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK1_RDCTL_WAIT_MASK)) |
                    FLCTL_BANK1_RDCTL_WAIT_1 ;

        /* Step 3: Configure HFXT to use 48MHz crystal, source to MCLK & SMCLK*/


            PJ->SEL0 |= BIT2 | BIT3;                // Configure PJ.2/3 for HFXT function
            PJ->SEL1 &= ~(BIT2 | BIT3);

            CS->KEY = CS_KEY_VAL ;                  // Unlock CS module for register access
            CS->CTL2 |= CS_CTL2_HFXT_EN | CS_CTL2_HFXTFREQ_6 | CS_CTL2_HFXTDRIVE;
            while(CS->IFG & CS_IFG_HFXTIFG)
            CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;

       /* Select MCLK & SMCLK = HFXT, no divider */
            CS->CTL1 = CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK | CS_CTL1_SELS_MASK | CS_CTL1_DIVHS_MASK) |
                    CS_CTL1_SELM__HFXTCLK | CS_CTL1_SELS__HFXTCLK|  CS_CTL1_DIVS_2;

            CS->KEY = 0;                            // Lock CS module from unintended accesses

}
void dev_init(void)
{
    init_32k();
    init_48M();

}

void CS_IRQHandler(void)
{


    CS->KEY = CS_KEY_VAL ;                                 // Unlock CS module for register access

    // Loop until XT1, XT2 & DCO fault flag is cleared
    do
    {
    // Clear XT2,XT1,DCO fault flags
       CS->CLRIFG |= CS_CLRIFG_CLR_DCOR_OPNIFG | CS_CLRIFG_CLR_HFXTIFG |
               CS_CLRIFG_CLR_LFXTIFG | CS_CLRIFG_CLR_FCNTLFIFG;

       SYSCTL->NMI_CTLSTAT &= ~ SYSCTL_NMI_CTLSTAT_CS_SRC;


    } while ((SYSCTL->NMI_CTLSTAT | SYSCTL_NMI_CTLSTAT_CS_FLG)
            && (CS->IFG & CS_IFG_LFXTIFG));              // Test oscillator fault flag

    CS->KEY = 0;                                         // Lock CS module from unintended accesses
}