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 * Copyright (c) 2014, Texas Instruments Incorporated
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 *******************************************************************************
 * 
 *                       MSP430 CODE EXAMPLE DISCLAIMER
 *
 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
 * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
 * for an API functional library-approach to peripheral configuration.
 *
 * --/COPYRIGHT--*/
//******************************************************************************
// MSP430FR6x7x Demo - COMPE output Toggle in LPM4; input channel C12;
//                     Vcompare is compared against internal 2.0V reference
//
// Description: Use CompE and internal reference to determine if input'Vcompare'
// is high or low.  When Vcompare exceeds 2.0V COUT goes high and when Vcompare
// is less than 2.0V then COUT goes low.
//
//                MSP430FR6972
//             ------------------
//         /|\|                  |
//          | |                  |
//          --|RST       P9.4/C12|<--Vcompare
//            |                  |
//            |         P1.2/COUT|----> 'high'(Vcompare>2.0V); 'low'(Vcompare<2.0V)
//            |                  |
//
//   Andreas Dannenberg
//   Texas Instruments Inc.
//   September 2014
//   Built with IAR Embedded Workbench V5.60 & Code Composer Studio V6.0
//******************************************************************************
#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

  // Configure Comp_E C12
  P9SEL1 |= BIT5;
  P9SEL0 |= BIT5;                           // Select C12 function on P9.5

  // Configure Comp_E COUT
  P1SEL1 |= BIT2;
  P1SEL0 &= ~(BIT2);
  P1DIR |= BIT2;                            // Select COUT function on P1.2

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // Setup Comparator_E
  CECTL0 = CEIPEN | CEIPSEL_12;             // Enable V+, input channel CE12
  CECTL1 = CEPWRMD_1;                       // normal power mode
  CECTL2 = CEREFL_2 | CERS_3 | CERSEL;      // VREF is applied to -terminal
                                            // R-ladder off; bandgap ref voltage
                                            // supplied to ref amplifier to get Vcref=2.0V
  CECTL3 = BITC;                            // Input Buffer Disable @P9.5/CE12
  CECTL1 |= CEON;                           // Turn On Comparator_E

  __delay_cycles(75);                       // delay for the reference to settle

  __bis_SR_register(LPM4_bits);             // Enter LPM4
  __no_operation();                         // For debug
}