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 * 
 *                       MSP430 CODE EXAMPLE DISCLAIMER
 *
 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
 * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
 * for an API functional library-approach to peripheral configuration.
 *
 * --/COPYRIGHT--*/
//******************************************************************************
//  MSP430FR6x7x Demo - COMPE Hysteresis, COUT Toggle in LPM4; High speed mode
//
//  Description: Use CompE and shared reference to determine if input 'Vcompare'
//  is high or low.  Shared reference is configured to generate hysteresis.
//  When Vcompare exceeds Vcc*3/4 COUT goes high and when Vcompare is less
//  than Vcc*1/4 then COUT goes low.
//
//                MSP430FR6972
//             ------------------
//         /|\|                  |
//          | |                  |
//          --|RST        P1.1/C1|<-- Vcompare
//            |                  |
//            |         P1.2/COUT|--> 'high'(Vcompare>Vcc*3/4); 'low'(Vcompare<Vcc*1/4)
//            |                  |
//
//   Andreas Dannenberg
//   Texas Instruments Inc.
//   September 2014
//   Built with IAR Embedded Workbench V5.60 & Code Composer Studio V6.0
//******************************************************************************
#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

  // Configure GPIO
  P1SEL1 |= BIT1;                           // P1.1 C1 for Vcompare
  P1SEL0 |= BIT1;
  P1DIR |= BIT2;                            // P1.2COUT output direction
  P1SEL1 |= BIT2;                           // Select COUT function on P1.2/COUT

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // Setup Comparator_E
  CECTL0 = CEIPEN | CEIPSEL_1;              // Enable V+, input channel CE1
  CECTL1 = CEPWRMD_0;                       // CEMRVS=0 => select VREF1 as ref when CEOUT
                                            // is high and VREF0 when CEOUT is low
                                            // High-Speed Power mode
  CECTL2 = CEREF13 | CERS_1 | CERSEL | CEREF04 | CEREF03;  // VRef is applied to -terminal
                                            // VREF1 is Vcc*1/4
                                            // VREF0 is Vcc*3/4

  CECTL3 = BIT1;                            // Input Buffer Disable @P1.1/C1
  CECTL1 |= CEON;                           // Turn On ComparatorE

  __delay_cycles(75);                       // delay for the reference to settle

  __bis_SR_register(LPM4_bits);             // Go to LPM4
  __no_operation();                         // For debug
}