#include "ti/devices/msp432p4xx/inc/msp.h"

int main(void)
{
    WDT_A->CTL = WDT_A_CTL_PW |             // Stop watchdog timer
            WDT_A_CTL_HOLD;

    P2->SEL0 |= BIT0 | BIT1 | BIT2 | BIT3;  // set 4-SPI pin as second function

    CS->KEY = CS_KEY_VAL ;                  // Unlock CS module for register access
    CS->CTL0 = 0;                           // Reset tuning parameters
    CS->CTL0 = CS_CTL0_DCORSEL_3;           // Set DCO to 12MHz (nominal, center of 8-16MHz range)
    // Select ACLK = REFO, SMCLK = MCLK = DCO
    CS->CTL1 = CS_CTL1_SELA_2 | CS_CTL1_SELS_3 | CS_CTL1_SELM_3;
    CS->KEY = 0;                            // Lock CS module from unintended accesses

    EUSCI_A1->CTLW0 |= EUSCI_A_CTLW0_SWRST; // Put state machine in reset
                                            // 4-pin, 8-bit SPI slave
    EUSCI_A1->CTLW0 = EUSCI_A_CTLW0_SWRST |
            EUSCI_A_CTLW0_SYNC |            // Synchronous mode
            EUSCI_A_CTLW0_CKPL |            // Clock polarity high
            EUSCI_A_CTLW0_MSB |             // MSB first
            EUSCI_A_CTLW0_MODE_1 |          // 4-pin SPI mode
            EUSCI_A_CTLW0_STEM |            // STE mode select
            EUSCI_A_CTLW0_SSEL__SMCLK;       // ACLK
    EUSCI_A1->BRW = 0x0018;                   // /2,fBitClock = fBRCLK/(UCBRx+1).
    EUSCI_A1->CTLW0 &= ~EUSCI_A_CTLW0_SWRST;// **Initialize USCI state machine**
    EUSCI_A1->IE |= EUSCI_A_IE_RXIE;        // Enable USCI_A1 RX interrupt

    // Remain in LPM on exit from ISR
    SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;

    // Ensures SLEEPONEXIT takes effect immediately
    __DSB();

    // Enable global interrupt
    __enable_irq();

    // Enable eUSCI_A1 interrupt in NVIC module
    NVIC->ISER[0] = 1 << ((EUSCIA1_IRQn) & 31);

    // Enter LPM0
    __sleep();

    __no_operation();                       // for debug
}

// SPI interrupt service routine
void EUSCIA1_IRQHandler(void)
{
    if (EUSCI_A1->IFG & EUSCI_A_IFG_RXIFG)
    {
        // USCI_A1 TX buffer ready?
        while (!(EUSCI_A1->IFG & EUSCI_A_IFG_TXIFG));

        // Echo received data
        EUSCI_A1->TXBUF = EUSCI_A1->RXBUF;
    }
}