#include "DSP2803x_Device.h" // DSP28 Headerfile Include File #include "DSP2803x_Examples.h" // DSP28 Examples Include File void caninit(void) // Initialize eCAN-A module { struct ECAN_REGS ECanaShadow; EALLOW; // EALLOW enables access to protected bits ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; ECanaShadow.CANTIOC.bit.TXFUNC = 1; ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; ECanaShadow.CANRIOC.bit.RXFUNC = 1; ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.SCB = 1; ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; /* Configure bit timing parameters for eCANA*/ ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; // Wait until the CPU has been granted permission to change the configuration registers do { ECanaShadow.CANES.all = ECanaRegs.CANES.all; } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set.. ECanaShadow.CANBTC.all = 0; /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps See Note at end of file. */ ECanaShadow.CANBTC.bit.BRPREG = 2; ECanaShadow.CANBTC.bit.TSEG2REG = 1; ECanaShadow.CANBTC.bit.TSEG1REG = 6; ECanaShadow.CANBTC.bit.SAM = 1; ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; // Wait until the CPU no longer has permission to change the configuration registers do { ECanaShadow.CANES.all = ECanaRegs.CANES.all; } while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared.. // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again // as a matter of precaution. ECanaRegs.CANTRR.all=0xffffffff; do { ECanaShadow.CANTRS.all = ECanaRegs.CANTRS.all; } while(ECanaShadow.CANTRS.all != 0 ); ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */ ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */ ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */ ECanaRegs.CANGIF1.all = 0xFFFFFFFF; /* Disable all Mailboxes */ ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs // Mailboxs can be written to 16-bits or 32-bits at a time // Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15 ECanaMboxes.MBOX0.MSGID.all = 0x80000000; ECanaMboxes.MBOX1.MSGID.all = 0x80000001; ECanaMboxes.MBOX2.MSGID.all = 0x80000002; ECanaMboxes.MBOX3.MSGID.all = 0x80000003; ECanaMboxes.MBOX4.MSGID.all = 0x80000004; ECanaMboxes.MBOX5.MSGID.all = 0x80000005; ECanaMboxes.MBOX6.MSGID.all = 0x80000006; ECanaMboxes.MBOX7.MSGID.all = 0x80000007; ECanaMboxes.MBOX8.MSGID.all = 0x80000008; ECanaMboxes.MBOX9.MSGID.all = 0x80000009; ECanaMboxes.MBOX10.MSGID.all = 0x8000000A; ECanaMboxes.MBOX11.MSGID.all = 0x8000000B; ECanaMboxes.MBOX12.MSGID.all = 0x8000000C; ECanaMboxes.MBOX13.MSGID.all = 0x8000000D; ECanaMboxes.MBOX14.MSGID.all = 0x8000000E; ECanaMboxes.MBOX15.MSGID.all = 0x8000000F; // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31 ECanaMboxes.MBOX16.MSGID.all = 0x81111110; ECanaMboxes.MBOX17.MSGID.all = 0x81111111; ECanaMboxes.MBOX18.MSGID.all = 0x81111112; ECanaMboxes.MBOX19.MSGID.all = 0x81111113; ECanaMboxes.MBOX20.MSGID.all = 0x81111114; ECanaMboxes.MBOX21.MSGID.all = 0x81111115; ECanaMboxes.MBOX22.MSGID.all = 0x81111116; ECanaMboxes.MBOX23.MSGID.all = 0x81111117; ECanaMboxes.MBOX24.MSGID.all = 0x81111118; ECanaMboxes.MBOX25.MSGID.all = 0x81111119; ECanaMboxes.MBOX26.MSGID.all = 0x8111111A; ECanaMboxes.MBOX27.MSGID.all = 0x8111111B; ECanaMboxes.MBOX28.MSGID.all = 0x8111111C; ECanaMboxes.MBOX29.MSGID.all = 0x8111111D; ECanaMboxes.MBOX30.MSGID.all = 0x8111111E; ECanaMboxes.MBOX31.MSGID.all = 0x8111111F; // Specify that 8 bits will be sent/received ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8; ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8; // Configure Mailboxes 0-15 as Tx, 16-31 as Rx // Since this write is to the entire register (instead of a bit // field) a shadow register is not required. ECanaRegs.CANMD.all = 0xFFFF0000; // Enable all Mailboxes */ // Since this write is to the entire register (instead of a bit // field) a shadow register is not required. ECanaRegs.CANME.all = 0xFFFFFFFF; // EDIS; } //--------------------------------------------------------------------------- // Example: InitECanGpio: //--------------------------------------------------------------------------- // This function initializes GPIO pins to function as eCAN pins // // Each GPIO pin can be configured as a GPIO pin or up to 3 different // peripheral functional pins. By default all pins come up as GPIO // inputs after reset. // // Caution: // Only one GPIO pin should be enabled for CANTXA operation. // Only one GPIO pin shoudl be enabled for CANRXA operation. // Comment out other unwanted lines. /* Note: Bit timing parameters must be chosen based on the network parameters such as the sampling point desired and the propagation delay of the network. The propagation delay is a function of length of the cable, delay introduced by the transceivers and opto/galvanic-isolators (if any). The parameters used in this file must be changed taking into account the above mentioned factors in order to arrive at the bit-timing parameters suitable for a network. */ //=========================================================================== // End of file. //===========================================================================