7 // TI File $Revision: /main/2 $ // Checkin $Date: July 30, 2009 18:44:22 $ //########################################################################### // Filename: Example_28xEcan_A_to_B_Xmit.c // // Description: eCANA-1 to eCANA2 Transmit loop // // ASSUMPTIONS: // // This program requires the DSP2833x header files. // // The CAN ports A of the two 2833x DSP need to be connected // to each other (via CAN transceivers)0 // // Transmitter end- eCANA1 is on GPIO19 (CANTXA) and // GPIO18 (CANRXA) // // Reciever end- eCANA2 is on GPIO19 (CANTXB) and // GPIO18 (CANRXB) // // As supplied, this project is configured for "boot to SARAM" // operation. The 2833x Boot Mode table is shown below. // For information on configuring the boot mode of an eZdsp, // please refer to the documentation included with the eZdsp, // // $Boot_Table: // // GPIO87 GPIO86 GPIO85 GPIO84 // XA15 XA14 XA13 XA12 // PU PU PU PU // ========================================== // 1 1 1 1 Jump to Flash // 1 1 1 0 SCI-A boot // 1 1 0 1 SPI-A boot // 1 1 0 0 I2C-A boot // 1 0 1 1 eCAN-A boot // 1 0 1 0 McBSP-A boot // 1 0 0 1 Jump to XINTF x16 // 1 0 0 0 Jump to XINTF x32 // 0 1 1 1 Jump to OTP // 0 1 1 0 Parallel GPIO I/O boot // 0 1 0 1 Parallel XINTF boot // 0 1 0 0 Jump to SARAM <- "boot to SARAM" // 0 0 1 1 Branch to check boot mode // 0 0 1 0 Boot to flash, bypass ADC cal // 0 0 0 1 Boot to SARAM, bypass ADC cal // 0 0 0 0 Boot to SCI-A, bypass ADC cal // Boot_Table_End$ // // DESCRIPTION: // // This example TRANSMITS data from MAILBOX5, CANA on DSP1 to another DS2P CANA module MAILBOX1 // This program could either loop forever or transmit "n" # of times, // where "n" is the TXCOUNT value. // // ########################################################################### #include "DSP28x_Project.h" // Prototype statements for functions found within this file. Uint16 loopcount =0; // Global Variables /* Create a shadow register structure for the CAN control registers. This is needed, since, only 32-bit access is allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents. This is especially true while writing to a bit (or group of bits) among bits 16 - 31 */ struct ECAN_REGS ECanbShadow; main() { // Initialize System Control registers, PLL, WatchDog, Clocks to default state: // This function is found in the DSP28_SysCtrl.c file. InitSysCtrl(); // Initialise the physical pins of the DSP //* Initialize the CAN module */ InitECan(); /* Write to the MSGID field */ ECanbMboxes.MBOX1.MSGID.all = 0x00500000; ECanbMboxes.MBOX1.MSGID.bit.IDE = 0; // standard Identifier /* Configure Mailbox under test as a Transmit mailbox */ ECanbShadow.CANMD.all = ECanbRegs.CANMD.all; ECanbShadow.CANMD.bit.MD1 = 0; ECanbRegs.CANMD.all = ECanbShadow.CANMD.all; /* Enable Mailbox under test */ ECanbShadow.CANME.all = ECanbRegs.CANME.all; ECanbShadow.CANME.bit.ME1 = 1; ECanbRegs.CANME.all = ECanbShadow.CANME.all; /* Write to DLC field in Master Control reg */ ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8; ECanbMboxes.MBOX1.MDL.all = 0x0000008A; ECanbMboxes.MBOX1.MDH.all = 0x0000008A; /* Begin transmitting */ for(;;) { ECanbShadow.CANTRS.all = 0; ECanbShadow.CANTRS.bit.TRS1 = 1; // Set TRS for mailbox under test ECanbRegs.CANTRS.all = ECanbShadow.CANTRS.all; do { ECanbShadow.CANTA.all = ECanbRegs.CANTA.all; } while(ECanbShadow.CANTA.bit.TA1 == 0 ); // Wait for TA5 bit to be set.. ECanbShadow.CANTA.all = 0; ECanbShadow.CANTA.bit.TA1 = 1; // Clear TA5 ECanbRegs.CANTA.all = ECanbShadow.CANTA.all; loopcount ++; } asm(" ESTOP0"); // Stop here }