/* * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include "board.h" //***************************************************************************** // // Board Configurations // Initializes the rest of the modules. // Call this function in your application if you wish to do all module // initialization. // If you wish to not use some of the initializations, instead of the // Board_init use the individual Module_inits // //***************************************************************************** void Board_init() { EALLOW; PinMux_init(); INPUTXBAR_init(); SYNC_init(); ASYSCTL_init(); CLA_init(); MEMCFG_init(); ADC_init(); CAN_init(); CMPSS_init(); CPUTIMER_init(); DAC_init(); ECAP_init(); EPWM_init(); GPIO_init(); SCI_init(); EDIS; } //***************************************************************************** // // PINMUX Configurations // //***************************************************************************** void PinMux_init() { // // PinMux for modules assigned to CPU1 // // // ANALOG -> myANALOGPinMux0 Pinmux // // Analog PinMux for A0/B15/C15/DACA_OUT GPIO_setPinConfig(GPIO_231_GPIO231); // AIO -> Analog mode selected GPIO_setAnalogMode(231, GPIO_ANALOG_ENABLED); // Analog PinMux for A1/B7/DACB_OUT GPIO_setPinConfig(GPIO_232_GPIO232); // AIO -> Analog mode selected GPIO_setAnalogMode(232, GPIO_ANALOG_ENABLED); // Analog PinMux for A10/B1/C10 GPIO_setPinConfig(GPIO_230_GPIO230); // AIO -> Analog mode selected GPIO_setAnalogMode(230, GPIO_ANALOG_ENABLED); // Analog PinMux for A11/B10/C0 GPIO_setPinConfig(GPIO_237_GPIO237); // AIO -> Analog mode selected GPIO_setAnalogMode(237, GPIO_ANALOG_ENABLED); // Analog PinMux for A12, C1 GPIO_setPinConfig(GPIO_238_GPIO238); // AIO -> Analog mode selected GPIO_setAnalogMode(238, GPIO_ANALOG_ENABLED); // Analog PinMux for A14/B14/C4 GPIO_setPinConfig(GPIO_239_GPIO239); // AIO -> Analog mode selected GPIO_setAnalogMode(239, GPIO_ANALOG_ENABLED); // Analog PinMux for A15, C7/B9 GPIO_setPinConfig(GPIO_233_GPIO233); // AIO -> Analog mode selected GPIO_setAnalogMode(233, GPIO_ANALOG_ENABLED); // Analog PinMux for A2/B6/C9 GPIO_setPinConfig(GPIO_224_GPIO224); // AIO -> Analog mode selected GPIO_setAnalogMode(224, GPIO_ANALOG_ENABLED); // Analog PinMux for A3, B3/VDAC, C5 GPIO_setPinConfig(GPIO_242_GPIO242); // AIO -> Analog mode selected GPIO_setAnalogMode(242, GPIO_ANALOG_ENABLED); // Analog PinMux for A4/B8, C14 GPIO_setPinConfig(GPIO_225_GPIO225); // AIO -> Analog mode selected GPIO_setAnalogMode(225, GPIO_ANALOG_ENABLED); // Analog PinMux for A5, C2/B12 GPIO_setPinConfig(GPIO_244_GPIO244); // AIO -> Analog mode selected GPIO_setAnalogMode(244, GPIO_ANALOG_ENABLED); // Analog PinMux for A6 GPIO_setPinConfig(GPIO_228_GPIO228); // AIO -> Analog mode selected GPIO_setAnalogMode(228, GPIO_ANALOG_ENABLED); // Analog PinMux for A8, B0/C11 GPIO_setPinConfig(GPIO_241_GPIO241); // AIO -> Analog mode selected GPIO_setAnalogMode(241, GPIO_ANALOG_ENABLED); // Analog PinMux for A9, B4/C8 GPIO_setPinConfig(GPIO_227_GPIO227); // AIO -> Analog mode selected GPIO_setAnalogMode(227, GPIO_ANALOG_ENABLED); // Analog PinMux for B2/C6 GPIO_setPinConfig(GPIO_226_GPIO226); // AIO -> Analog mode selected GPIO_setAnalogMode(226, GPIO_ANALOG_ENABLED); // Analog PinMux for C3/A7 GPIO_setPinConfig(GPIO_245_GPIO245); // AIO -> Analog mode selected GPIO_setAnalogMode(245, GPIO_ANALOG_ENABLED); // // CANA -> myCAN0 Pinmux // GPIO_setPinConfig(myCAN0_CANRX_PIN_CONFIG); GPIO_setPadConfig(myCAN0_CANRX_GPIO, GPIO_PIN_TYPE_STD | GPIO_PIN_TYPE_PULLUP); GPIO_setQualificationMode(myCAN0_CANRX_GPIO, GPIO_QUAL_ASYNC); GPIO_setPinConfig(myCAN0_CANTX_PIN_CONFIG); GPIO_setPadConfig(myCAN0_CANTX_GPIO, GPIO_PIN_TYPE_STD | GPIO_PIN_TYPE_PULLUP); GPIO_setQualificationMode(myCAN0_CANTX_GPIO, GPIO_QUAL_ASYNC); // // EPWM1 -> myEPWM0 Pinmux // GPIO_setPinConfig(myEPWM0_EPWMA_PIN_CONFIG); GPIO_setPadConfig(myEPWM0_EPWMA_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(myEPWM0_EPWMA_GPIO, GPIO_QUAL_SYNC); GPIO_setPinConfig(myEPWM0_EPWMB_PIN_CONFIG); GPIO_setPadConfig(myEPWM0_EPWMB_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(myEPWM0_EPWMB_GPIO, GPIO_QUAL_SYNC); // // EPWM2 -> myEPWM1 Pinmux // GPIO_setPinConfig(myEPWM1_EPWMA_PIN_CONFIG); GPIO_setPadConfig(myEPWM1_EPWMA_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(myEPWM1_EPWMA_GPIO, GPIO_QUAL_SYNC); GPIO_setPinConfig(myEPWM1_EPWMB_PIN_CONFIG); GPIO_setPadConfig(myEPWM1_EPWMB_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(myEPWM1_EPWMB_GPIO, GPIO_QUAL_SYNC); // // EPWM3 -> CLA_Clock_PWM Pinmux // // GPIO4 -> DIS_LLC_GPIO Pinmux GPIO_setPinConfig(GPIO_4_GPIO4); // GPIO5 -> N_WINDOW_input Pinmux GPIO_setPinConfig(GPIO_5_GPIO5); // GPIO9 -> P_WINDOW_input Pinmux GPIO_setPinConfig(GPIO_9_GPIO9); // GPIO10 -> INRUSH_CNTRL_GPIO Pinmux GPIO_setPinConfig(GPIO_10_GPIO10); // GPIO11 -> ENABLE_CAN Pinmux GPIO_setPinConfig(GPIO_11_GPIO11); // GPIO16 -> DBA_STB_N Pinmux GPIO_setPinConfig(GPIO_16_GPIO16); // GPIO33 -> DBA_CAN_ERROR Pinmux GPIO_setPinConfig(GPIO_33_GPIO33); // GPIO17 -> HW_DISABLE_GPIO Pinmux GPIO_setPinConfig(GPIO_17_GPIO17); // GPIO24 -> DISABLE_GPIO Pinmux GPIO_setPinConfig(GPIO_24_GPIO24); // GPIO7 -> DIS_SR_CON_GPIO Pinmux GPIO_setPinConfig(GPIO_7_GPIO7); // GPIO22 -> FAN_ON_GPIO Pinmux GPIO_setPinConfig(GPIO_22_GPIO22); // GPIO8 -> DIS_PFC_GPIO Pinmux GPIO_setPinConfig(GPIO_8_GPIO8); // GPIO6 -> GPIO6_DEBUG Pinmux GPIO_setPinConfig(GPIO_6_GPIO6); // // SCIB -> mySCI0 Pinmux // GPIO_setPinConfig(mySCI0_SCIRX_PIN_CONFIG); GPIO_setPadConfig(mySCI0_SCIRX_GPIO, GPIO_PIN_TYPE_STD | GPIO_PIN_TYPE_PULLUP); GPIO_setQualificationMode(mySCI0_SCIRX_GPIO, GPIO_QUAL_ASYNC); GPIO_setPinConfig(mySCI0_SCITX_PIN_CONFIG); GPIO_setPadConfig(mySCI0_SCITX_GPIO, GPIO_PIN_TYPE_STD | GPIO_PIN_TYPE_PULLUP); GPIO_setQualificationMode(mySCI0_SCITX_GPIO, GPIO_QUAL_ASYNC); } //***************************************************************************** // // ADC Configurations // //***************************************************************************** void ADC_init(){ myADC1_init(); } void myADC1_init(){ // // ADC Initialization: Write ADC configurations and power up the ADC // // Configures the ADC module's offset trim // ADC_setOffsetTrimAll(ADC_REFERENCE_INTERNAL,ADC_REFERENCE_3_3V); // // Configures the analog-to-digital converter module prescaler. // ADC_setPrescaler(myADC1_BASE, ADC_CLK_DIV_2_0); // // Sets the timing of the end-of-conversion pulse // ADC_setInterruptPulseMode(myADC1_BASE, ADC_PULSE_END_OF_ACQ_WIN); // // Sets the timing of early interrupt generation. // ADC_setInterruptCycleOffset(myADC1_BASE, 0U); // // Powers up the analog-to-digital converter core. // ADC_enableConverter(myADC1_BASE); // // Delay for 1ms to allow ADC time to power up // DEVICE_DELAY_US(5000); // // SOC Configuration: Setup ADC EPWM channel and trigger settings // // Disables SOC burst mode. // ADC_disableBurstMode(myADC1_BASE); // // Sets the priority mode of the SOCs. // ADC_setSOCPriority(myADC1_BASE, ADC_PRI_ALL_ROUND_ROBIN); // // Start of Conversion 0 Configuration // // // Configures a start-of-conversion (SOC) in the ADC and its interrupt SOC trigger. // SOC number : 0 // Trigger : ADC_TRIGGER_EPWM1_SOCA // Channel : ADC_CH_ADCIN12 // Sample Window : 9 SYSCLK cycles // Interrupt Trigger: ADC_INT_SOC_TRIGGER_NONE // ADC_setupSOC(myADC1_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA, ADC_CH_ADCIN12, 9U); ADC_setInterruptSOCTrigger(myADC1_BASE, ADC_SOC_NUMBER0, ADC_INT_SOC_TRIGGER_NONE); } //***************************************************************************** // // ASYSCTL Configurations // //***************************************************************************** void ASYSCTL_init(){ // // asysctl initialization // // Enables the temperature sensor output to the ADC. // ASysCtl_enableTemperatureSensor(); DEVICE_DELAY_US(500); // // Locks the temperature sensor control register. // ASysCtl_lockTemperatureSensor(); // // Set the analog voltage reference selection to internal. // ASysCtl_setAnalogReferenceInternal( ASYSCTL_VREFHI ); // // Set the internal analog voltage reference selection to 1.65V. // ASysCtl_setAnalogReference1P65( ASYSCTL_VREFHI ); } //***************************************************************************** // // CAN Configurations // //***************************************************************************** void CAN_init(){ myCAN0_init(); } void myCAN0_init(){ CAN_initModule(myCAN0_BASE); // // Refer to the Driver Library User Guide for information on how to set // tighter timing control. Additionally, consult the device data sheet // for more information about the CAN module clocking. // CAN_setBitTiming(myCAN0_BASE, 9, 0, 14, 7, 3); // // Enable CAN Interrupts // CAN_enableInterrupt(myCAN0_BASE, CAN_INT_ERROR|CAN_INT_IE0); CAN_setInterruptMux(myCAN0_BASE, 0); // // The CAN module is not started in this function. // The application SW must call the CAN_startModule when needed. // CAN_startModule(myCAN0_BASE); // } //***************************************************************************** // // CLA Configurations // //***************************************************************************** void myCLA0_init(){ // // Configure all CLA task vectors // On Type-1 and Type-2 CLAs the MVECT registers accept full 16-bit task addresses as // opposed to offsets used on older Type-0 CLAs // #pragma diag_suppress=770 // // CLA Task 1 // CLA_mapTaskVector(myCLA0_BASE, CLA_MVECT_1, (uint16_t)&Cla1Task1); CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_ADCA1); #pragma diag_warning=770 // // Enable the IACK instruction to start a task on CLA in software // for all 8 CLA tasks. Also, globally enable all 8 tasks (or a // subset of tasks) by writing to their respective bits in the // MIER register // CLA_enableIACK(myCLA0_BASE); CLA_enableTasks(myCLA0_BASE, CLA_TASKFLAG_1 ); } void CLA_init() { #ifdef _FLASH #ifndef CMDTOOL // Linker command tool is not used extern uint32_t Cla1ProgRunStart, Cla1ProgLoadStart, Cla1ProgLoadSize; extern uint32_t Cla1ConstRunStart, Cla1ConstLoadStart, Cla1ConstLoadSize; // // Copy the program and constants from FLASH to RAM before configuring // the CLA // memcpy((uint32_t *)&Cla1ProgRunStart, (uint32_t *)&Cla1ProgLoadStart, (uint32_t)&Cla1ProgLoadSize); memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart, (uint32_t)&Cla1ConstLoadSize ); #endif //CMDTOOL #endif //_FLASH myCLA0_init(); } //***************************************************************************** // // CMPSS Configurations // //***************************************************************************** void CMPSS_init(){ myCMPSS0_init(); myCMPSS1_init(); myCMPSS2_init(); myCMPSS3_init(); } void myCMPSS0_init(){ // // Select the value for CMP1HPMXSEL. // ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1,1U); // // Select the value for CMP1LPMXSEL. // ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1,1U); // // Sets the configuration for the high comparator. // CMPSS_configHighComparator(myCMPSS0_BASE,(CMPSS_INSRC_DAC | CMPSS_OR_ASYNC_OUT_W_FILT)); // // Sets the configuration for the low comparator. // CMPSS_configLowComparator(myCMPSS0_BASE,(CMPSS_INSRC_DAC | CMPSS_INV_INVERTED | CMPSS_OR_ASYNC_OUT_W_FILT)); // // Sets the configuration for the internal comparator DACs. // CMPSS_configDAC(myCMPSS0_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW)); // // Sets the value of the internal DAC of the high comparator. // CMPSS_setDACValueHigh(myCMPSS0_BASE,3300U); // // Sets the value of the internal DAC of the low comparator. // CMPSS_setDACValueLow(myCMPSS0_BASE,808U); // // Configures the digital filter of the high comparator. // CMPSS_configFilterHigh(myCMPSS0_BASE, 0U, 1U, 1U); // // Configures the digital filter of the low comparator. // CMPSS_configFilterLow(myCMPSS0_BASE, 0U, 1U, 1U); // // Initializes the digital filter of the high comparator. // CMPSS_initFilterHigh(myCMPSS0_BASE); // // Initializes the digital filter of the low comparator. // CMPSS_initFilterLow(myCMPSS0_BASE); // // Sets the output signal configuration for the high comparator. // CMPSS_configOutputsHigh(myCMPSS0_BASE,(CMPSS_TRIPOUT_LATCH | CMPSS_TRIP_LATCH)); // // Sets the output signal configuration for the low comparator. // CMPSS_configOutputsLow(myCMPSS0_BASE,(CMPSS_TRIPOUT_LATCH | CMPSS_TRIP_LATCH)); // // Sets the comparator hysteresis settings. // CMPSS_setHysteresis(myCMPSS0_BASE,4U); // // Configures the comparator subsystem's ramp generator. // CMPSS_configRamp(myCMPSS0_BASE,0U,0U,0U,1U,true); // // Disables reset of HIGH comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCHigh(myCMPSS0_BASE); // // Disables reset of LOW comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCLow(myCMPSS0_BASE); // // Sets the ePWM module blanking signal that holds trip in reset. // CMPSS_configBlanking(myCMPSS0_BASE,1U); // // Disables an ePWM blanking signal from holding trip in reset. // CMPSS_disableBlanking(myCMPSS0_BASE); // // Configures whether or not the digital filter latches are reset by PWMSYNC // CMPSS_configLatchOnPWMSYNC(myCMPSS0_BASE,false,false); // // Enables the CMPSS module. // CMPSS_enableModule(myCMPSS0_BASE); // // Delay for CMPSS DAC to power up. // DEVICE_DELAY_US(500); // // Causes a software reset of the high comparator digital filter output latch. // CMPSS_clearFilterLatchHigh(myCMPSS0_BASE); // // Causes a software reset of the low comparator digital filter output latch. // CMPSS_clearFilterLatchLow(myCMPSS0_BASE); } void myCMPSS1_init(){ // // Select the value for CMP2HPMXSEL. // ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_2,1U); // // Select the value for CMP2LPMXSEL. // ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_2,1U); // // Sets the configuration for the high comparator. // CMPSS_configHighComparator(myCMPSS1_BASE,(CMPSS_INSRC_DAC | CMPSS_OR_ASYNC_OUT_W_FILT)); // // Sets the configuration for the low comparator. // CMPSS_configLowComparator(myCMPSS1_BASE,(CMPSS_INSRC_DAC)); // // Sets the configuration for the internal comparator DACs. // CMPSS_configDAC(myCMPSS1_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW)); // // Sets the value of the internal DAC of the high comparator. // CMPSS_setDACValueHigh(myCMPSS1_BASE,3350U); // // Sets the value of the internal DAC of the low comparator. // CMPSS_setDACValueLow(myCMPSS1_BASE,0U); // // Configures the digital filter of the high comparator. // CMPSS_configFilterHigh(myCMPSS1_BASE, 0U, 3U, 2U); // // Configures the digital filter of the low comparator. // CMPSS_configFilterLow(myCMPSS1_BASE, 0U, 1U, 1U); // // Initializes the digital filter of the high comparator. // CMPSS_initFilterHigh(myCMPSS1_BASE); // // Sets the output signal configuration for the high comparator. // CMPSS_configOutputsHigh(myCMPSS1_BASE,(CMPSS_TRIPOUT_LATCH | CMPSS_TRIP_LATCH)); // // Sets the output signal configuration for the low comparator. // CMPSS_configOutputsLow(myCMPSS1_BASE,(CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_ASYNC_COMP)); // // Sets the comparator hysteresis settings. // CMPSS_setHysteresis(myCMPSS1_BASE,4U); // // Configures the comparator subsystem's ramp generator. // CMPSS_configRamp(myCMPSS1_BASE,0U,0U,0U,1U,true); // // Disables reset of HIGH comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCHigh(myCMPSS1_BASE); // // Disables reset of LOW comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCLow(myCMPSS1_BASE); // // Sets the ePWM module blanking signal that holds trip in reset. // CMPSS_configBlanking(myCMPSS1_BASE,1U); // // Disables an ePWM blanking signal from holding trip in reset. // CMPSS_disableBlanking(myCMPSS1_BASE); // // Configures whether or not the digital filter latches are reset by PWMSYNC // CMPSS_configLatchOnPWMSYNC(myCMPSS1_BASE,false,false); // // Enables the CMPSS module. // CMPSS_enableModule(myCMPSS1_BASE); // // Delay for CMPSS DAC to power up. // DEVICE_DELAY_US(500); // // Causes a software reset of the high comparator digital filter output latch. // CMPSS_clearFilterLatchHigh(myCMPSS1_BASE); } void myCMPSS2_init(){ // // Select the value for CMP3HPMXSEL. // ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_3,4U); // // Select the value for CMP3LPMXSEL. // ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_3,5U); // // Sets the configuration for the high comparator. // CMPSS_configHighComparator(myCMPSS2_BASE,(CMPSS_INSRC_DAC | CMPSS_OR_ASYNC_OUT_W_FILT)); // // Sets the configuration for the low comparator. // CMPSS_configLowComparator(myCMPSS2_BASE,(CMPSS_INSRC_DAC | CMPSS_OR_ASYNC_OUT_W_FILT)); // // Sets the configuration for the internal comparator DACs. // CMPSS_configDAC(myCMPSS2_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW)); // // Sets the value of the internal DAC of the high comparator. // CMPSS_setDACValueHigh(myCMPSS2_BASE,4000U); // // Sets the value of the internal DAC of the low comparator. // CMPSS_setDACValueLow(myCMPSS2_BASE,3000U); // // Configures the digital filter of the high comparator. // CMPSS_configFilterHigh(myCMPSS2_BASE, 10U, 20U, 11U); // // Configures the digital filter of the low comparator. // CMPSS_configFilterLow(myCMPSS2_BASE, 0U, 3U, 2U); // // Initializes the digital filter of the high comparator. // CMPSS_initFilterHigh(myCMPSS2_BASE); // // Initializes the digital filter of the low comparator. // CMPSS_initFilterLow(myCMPSS2_BASE); // // Sets the output signal configuration for the high comparator. // CMPSS_configOutputsHigh(myCMPSS2_BASE,(CMPSS_TRIPOUT_LATCH | CMPSS_TRIP_LATCH)); // // Sets the output signal configuration for the low comparator. // CMPSS_configOutputsLow(myCMPSS2_BASE,(CMPSS_TRIPOUT_LATCH | CMPSS_TRIP_LATCH)); // // Sets the comparator hysteresis settings. // CMPSS_setHysteresis(myCMPSS2_BASE,4U); // // Configures the comparator subsystem's ramp generator. // CMPSS_configRamp(myCMPSS2_BASE,0U,0U,0U,1U,true); // // Disables reset of HIGH comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCHigh(myCMPSS2_BASE); // // Disables reset of LOW comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCLow(myCMPSS2_BASE); // // Sets the ePWM module blanking signal that holds trip in reset. // CMPSS_configBlanking(myCMPSS2_BASE,1U); // // Disables an ePWM blanking signal from holding trip in reset. // CMPSS_disableBlanking(myCMPSS2_BASE); // // Configures whether or not the digital filter latches are reset by PWMSYNC // CMPSS_configLatchOnPWMSYNC(myCMPSS2_BASE,false,false); // // Enables the CMPSS module. // CMPSS_enableModule(myCMPSS2_BASE); // // Delay for CMPSS DAC to power up. // DEVICE_DELAY_US(500); // // Causes a software reset of the high comparator digital filter output latch. // CMPSS_clearFilterLatchHigh(myCMPSS2_BASE); // // Causes a software reset of the low comparator digital filter output latch. // CMPSS_clearFilterLatchLow(myCMPSS2_BASE); } void myCMPSS3_init(){ // // Select the value for CMP4HPMXSEL. // ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_4,1U); // // Select the value for CMP4LPMXSEL. // ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_4,1U); // // Sets the configuration for the high comparator. // CMPSS_configHighComparator(myCMPSS3_BASE,(CMPSS_INSRC_DAC | CMPSS_OR_ASYNC_OUT_W_FILT)); // // Sets the configuration for the low comparator. // CMPSS_configLowComparator(myCMPSS3_BASE,(CMPSS_INSRC_DAC)); // // Sets the configuration for the internal comparator DACs. // CMPSS_configDAC(myCMPSS3_BASE,(CMPSS_DACVAL_SYSCLK | CMPSS_DACREF_VDDA | CMPSS_DACSRC_SHDW)); // // Sets the value of the internal DAC of the high comparator. // CMPSS_setDACValueHigh(myCMPSS3_BASE,3000U); // // Sets the value of the internal DAC of the low comparator. // CMPSS_setDACValueLow(myCMPSS3_BASE,0U); // // Configures the digital filter of the high comparator. // CMPSS_configFilterHigh(myCMPSS3_BASE, 0U, 3U, 2U); // // Configures the digital filter of the low comparator. // CMPSS_configFilterLow(myCMPSS3_BASE, 0U, 1U, 1U); // // Initializes the digital filter of the high comparator. // CMPSS_initFilterHigh(myCMPSS3_BASE); // // Sets the output signal configuration for the high comparator. // CMPSS_configOutputsHigh(myCMPSS3_BASE,(CMPSS_TRIPOUT_LATCH | CMPSS_TRIP_LATCH)); // // Sets the output signal configuration for the low comparator. // CMPSS_configOutputsLow(myCMPSS3_BASE,(CMPSS_TRIPOUT_ASYNC_COMP | CMPSS_TRIP_ASYNC_COMP)); // // Sets the comparator hysteresis settings. // CMPSS_setHysteresis(myCMPSS3_BASE,4U); // // Configures the comparator subsystem's ramp generator. // CMPSS_configRamp(myCMPSS3_BASE,0U,0U,0U,1U,true); // // Disables reset of HIGH comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCHigh(myCMPSS3_BASE); // // Disables reset of LOW comparator digital filter output latch on PWMSYNC // CMPSS_disableLatchResetOnPWMSYNCLow(myCMPSS3_BASE); // // Sets the ePWM module blanking signal that holds trip in reset. // CMPSS_configBlanking(myCMPSS3_BASE,1U); // // Disables an ePWM blanking signal from holding trip in reset. // CMPSS_disableBlanking(myCMPSS3_BASE); // // Configures whether or not the digital filter latches are reset by PWMSYNC // CMPSS_configLatchOnPWMSYNC(myCMPSS3_BASE,false,false); // // Enables the CMPSS module. // CMPSS_enableModule(myCMPSS3_BASE); // // Delay for CMPSS DAC to power up. // DEVICE_DELAY_US(500); // // Causes a software reset of the high comparator digital filter output latch. // CMPSS_clearFilterLatchHigh(myCMPSS3_BASE); } //***************************************************************************** // // CPUTIMER Configurations // //***************************************************************************** void CPUTIMER_init(){ myCPUTIMER0_init(); } void myCPUTIMER0_init(){ CPUTimer_setEmulationMode(myCPUTIMER0_BASE, CPUTIMER_EMULATIONMODE_RUNFREE); CPUTimer_setPreScaler(myCPUTIMER0_BASE, 0U); CPUTimer_setPeriod(myCPUTIMER0_BASE, 12000U); CPUTimer_disableInterrupt(myCPUTIMER0_BASE); CPUTimer_stopTimer(myCPUTIMER0_BASE); CPUTimer_reloadTimerCounter(myCPUTIMER0_BASE); } //***************************************************************************** // // DAC Configurations // //***************************************************************************** void DAC_init(){ myDAC0_init(); } void myDAC0_init(){ // // Set DAC reference voltage. // DAC_setReferenceVoltage(myDAC0_BASE, DAC_REF_ADC_VREFHI); // // Set DAC gain mode. // DAC_setGainMode(myDAC0_BASE, DAC_GAIN_TWO); // // Set DAC load mode. // DAC_setLoadMode(myDAC0_BASE, DAC_LOAD_SYSCLK); // // Enable the DAC output // DAC_enableOutput(myDAC0_BASE); // // Set the DAC shadow output // DAC_setShadowValue(myDAC0_BASE, 0U); // // Lock write-access to DAC Register // DAC_lockRegister(myDAC0_BASE, (DAC_LOCK_OUTPUT)); // // Delay for buffered DAC to power up. // DEVICE_DELAY_US(5000); } //***************************************************************************** // // ECAP Configurations // //***************************************************************************** void ECAP_init(){ myECAP0_init(); } void myECAP0_init(){ // // Disables time stamp capture. // ECAP_disableTimeStampCapture(myECAP0_BASE); // // Stops Time stamp counter. // ECAP_stopCounter(myECAP0_BASE); // // Sets eCAP in Capture mode. // ECAP_enableCaptureMode(myECAP0_BASE); // // Sets the capture mode. // ECAP_setCaptureMode(myECAP0_BASE,ECAP_CONTINUOUS_CAPTURE_MODE,ECAP_EVENT_1); // // Sets the Capture event prescaler. // ECAP_setEventPrescaler(myECAP0_BASE, 0U); // // Sets the Capture event polarity. // ECAP_setEventPolarity(myECAP0_BASE,ECAP_EVENT_1,ECAP_EVNT_RISING_EDGE); ECAP_setEventPolarity(myECAP0_BASE,ECAP_EVENT_2,ECAP_EVNT_RISING_EDGE); ECAP_setEventPolarity(myECAP0_BASE,ECAP_EVENT_3,ECAP_EVNT_RISING_EDGE); ECAP_setEventPolarity(myECAP0_BASE,ECAP_EVENT_4,ECAP_EVNT_RISING_EDGE); // // Configure counter reset on events // ECAP_enableCounterResetOnEvent(myECAP0_BASE,ECAP_EVENT_1); ECAP_disableCounterResetOnEvent(myECAP0_BASE,ECAP_EVENT_2); ECAP_disableCounterResetOnEvent(myECAP0_BASE,ECAP_EVENT_3); ECAP_disableCounterResetOnEvent(myECAP0_BASE,ECAP_EVENT_4); // // Select eCAP input. // ECAP_selectECAPInput(myECAP0_BASE,ECAP_INPUT_INPUTXBAR1); // // Sets a phase shift value count. // ECAP_setPhaseShiftCount(myECAP0_BASE,0U); // // Disable counter loading with phase shift value. // ECAP_disableLoadCounter(myECAP0_BASE); // // Configures Sync out signal mode. // ECAP_setSyncOutMode(myECAP0_BASE,ECAP_SYNC_OUT_SYNCI); // // Resets eCAP counters and flags. // ECAP_resetCounters(myECAP0_BASE); // // Configures emulation mode. // ECAP_setEmulationMode(myECAP0_BASE,ECAP_EMULATION_STOP); // // Set up the source for sync-in pulse.. // ECAP_setSyncInPulseSource(myECAP0_BASE,ECAP_SYNC_IN_PULSE_SRC_DISABLE); // // Starts Time stamp counter for myECAP0. // ECAP_startCounter(myECAP0_BASE); // // Enables time stamp capture for myECAP0. // ECAP_enableTimeStampCapture(myECAP0_BASE); // // Re-arms the eCAP module for myECAP0. // ECAP_reArm(myECAP0_BASE); } //***************************************************************************** // // EPWM Configurations // //***************************************************************************** void EPWM_init(){ EPWM_setClockPrescaler(myEPWM0_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); EPWM_setTimeBasePeriod(myEPWM0_BASE, 925); EPWM_setupEPWMLinks(myEPWM0_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); EPWM_setTimeBaseCounter(myEPWM0_BASE, 0); EPWM_setTimeBaseCounterMode(myEPWM0_BASE, EPWM_COUNTER_MODE_UP_DOWN); EPWM_disablePhaseShiftLoad(myEPWM0_BASE); EPWM_setPhaseShift(myEPWM0_BASE, 0); EPWM_setCounterCompareValue(myEPWM0_BASE, EPWM_COUNTER_COMPARE_A, 50); EPWM_setCounterCompareShadowLoadMode(myEPWM0_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setupEPWMLinks(myEPWM0_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A); EPWM_setCounterCompareValue(myEPWM0_BASE, EPWM_COUNTER_COMPARE_B, 50); EPWM_setCounterCompareShadowLoadMode(myEPWM0_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setupEPWMLinks(myEPWM0_BASE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_B); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(myEPWM0_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setDeadBandDelayPolarity(myEPWM0_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); EPWM_setDeadBandDelayMode(myEPWM0_BASE, EPWM_DB_RED, true); EPWM_setRisingEdgeDelayCountShadowLoadMode(myEPWM0_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO); EPWM_setRisingEdgeDelayCount(myEPWM0_BASE, 60); EPWM_setDeadBandDelayMode(myEPWM0_BASE, EPWM_DB_FED, true); EPWM_setFallingEdgeDelayCountShadowLoadMode(myEPWM0_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO); EPWM_setFallingEdgeDelayCount(myEPWM0_BASE, 60); EPWM_setDeadBandOutputSwapMode(myEPWM0_BASE, EPWM_DB_OUTPUT_A, true); EPWM_setDeadBandOutputSwapMode(myEPWM0_BASE, EPWM_DB_OUTPUT_B, true); EPWM_setTripZoneAction(myEPWM0_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(myEPWM0_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); EPWM_setTripZoneAction(myEPWM0_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(myEPWM0_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(myEPWM0_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_DISABLE); EPWM_setTripZoneAction(myEPWM0_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_enableTripZoneSignals(myEPWM0_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT3); EPWM_selectDigitalCompareTripInput(myEPWM0_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH); EPWM_enableDigitalCompareTripCombinationInput(myEPWM0_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAH); EPWM_selectDigitalCompareTripInput(myEPWM0_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL); EPWM_enableDigitalCompareTripCombinationInput(myEPWM0_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAL); EPWM_setTripZoneDigitalCompareEventCondition(myEPWM0_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setDigitalCompareEventSyncMode(myEPWM0_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); EPWM_setDigitalCompareCBCLatchMode(myEPWM0_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_ENABLED); EPWM_selectDigitalCompareTripInput(myEPWM0_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH); EPWM_enableDigitalCompareTripCombinationInput(myEPWM0_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBH); EPWM_selectDigitalCompareTripInput(myEPWM0_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL); EPWM_enableDigitalCompareTripCombinationInput(myEPWM0_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBL); EPWM_setTripZoneDigitalCompareEventCondition(myEPWM0_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH); EPWM_setDigitalCompareEventSyncMode(myEPWM0_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); EPWM_setDigitalCompareCBCLatchMode(myEPWM0_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_ENABLED); EPWM_enableADCTrigger(myEPWM0_BASE, EPWM_SOC_A); EPWM_setADCTriggerSource(myEPWM0_BASE, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO); EPWM_setADCTriggerEventPrescale(myEPWM0_BASE, EPWM_SOC_A, 2); EPWM_enableADCTrigger(myEPWM0_BASE, EPWM_SOC_B); EPWM_setADCTriggerSource(myEPWM0_BASE, EPWM_SOC_B, EPWM_SOC_TBCTR_ZERO); EPWM_setADCTriggerEventPrescale(myEPWM0_BASE, EPWM_SOC_B, 2); HRPWM_setClockPrescaler(myEPWM1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); EPWM_setTimeBasePeriod(myEPWM1_BASE, 600); HRPWM_setTimeBaseCounter(myEPWM1_BASE, 0); HRPWM_setTimeBaseCounterMode(myEPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN); HRPWM_disablePhaseShiftLoad(myEPWM1_BASE); HRPWM_setPhaseShift(myEPWM1_BASE, 0); EPWM_setSyncInPulseSource(myEPWM1_BASE, EPWM_SYNC_IN_PULSE_SRC_DISABLE); EPWM_setCounterCompareValue(myEPWM1_BASE, EPWM_COUNTER_COMPARE_A, 300); HRPWM_setCounterCompareShadowLoadMode(myEPWM1_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD); EPWM_setCounterCompareValue(myEPWM1_BASE, EPWM_COUNTER_COMPARE_B, 300); HRPWM_setCounterCompareShadowLoadMode(myEPWM1_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD); HRPWM_setActionQualifierT1TriggerSource(myEPWM1_BASE, EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); HRPWM_setActionQualifierAction(myEPWM1_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); HRPWM_setDeadBandDelayPolarity(myEPWM1_BASE, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW); HRPWM_setDeadBandDelayMode(myEPWM1_BASE, EPWM_DB_RED, true); HRPWM_setRisingEdgeDelayCountShadowLoadMode(myEPWM1_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO); HRPWM_setRisingEdgeDelayCount(myEPWM1_BASE, 250); HRPWM_setDeadBandDelayMode(myEPWM1_BASE, EPWM_DB_FED, true); HRPWM_setFallingEdgeDeadBandDelayInput(myEPWM1_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO); HRPWM_setFallingEdgeDelayCount(myEPWM1_BASE, 250); HRPWM_setDeadBandOutputSwapMode(myEPWM1_BASE, EPWM_DB_OUTPUT_A, true); HRPWM_setDeadBandOutputSwapMode(myEPWM1_BASE, EPWM_DB_OUTPUT_B, true); HRPWM_setDeadBandCounterClock(myEPWM1_BASE, EPWM_DB_COUNTER_CLOCK_HALF_CYCLE); HRPWM_setTripZoneAction(myEPWM1_BASE, EPWM_TZ_ACTION_EVENT_TZA, EPWM_TZ_ACTION_LOW); HRPWM_setTripZoneAction(myEPWM1_BASE, EPWM_TZ_ACTION_EVENT_TZB, EPWM_TZ_ACTION_LOW); HRPWM_setTripZoneAction(myEPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT1, EPWM_TZ_ACTION_DISABLE); HRPWM_setTripZoneAction(myEPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCAEVT2, EPWM_TZ_ACTION_DISABLE); HRPWM_setTripZoneAction(myEPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT1, EPWM_TZ_ACTION_DISABLE); HRPWM_setTripZoneAction(myEPWM1_BASE, EPWM_TZ_ACTION_EVENT_DCBEVT2, EPWM_TZ_ACTION_DISABLE); EPWM_enableTripZoneSignals(myEPWM1_BASE, EPWM_TZ_SIGNAL_DCAEVT1 | EPWM_TZ_SIGNAL_DCBEVT1 | EPWM_TZ_SIGNAL_OSHT3); HRPWM_selectDigitalCompareTripInput(myEPWM1_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAH); HRPWM_enableDigitalCompareTripCombinationInput(myEPWM1_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAH); HRPWM_selectDigitalCompareTripInput(myEPWM1_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCAL); HRPWM_enableDigitalCompareTripCombinationInput(myEPWM1_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCAL); HRPWM_setTripZoneDigitalCompareEventCondition(myEPWM1_BASE, EPWM_TZ_DC_OUTPUT_A1, EPWM_TZ_EVENT_DCXH_HIGH); HRPWM_setDigitalCompareEventSyncMode(myEPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); (myEPWM1_BASE, EPWM_DC_MODULE_A, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_ENABLED); HRPWM_selectDigitalCompareTripInput(myEPWM1_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBH); HRPWM_enableDigitalCompareTripCombinationInput(myEPWM1_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBH); HRPWM_selectDigitalCompareTripInput(myEPWM1_BASE, EPWM_DC_TRIP_COMBINATION, EPWM_DC_TYPE_DCBL); HRPWM_enableDigitalCompareTripCombinationInput(myEPWM1_BASE, EPWM_DC_COMBINATIONAL_TRIPIN7 | EPWM_DC_COMBINATIONAL_TRIPIN8, EPWM_DC_TYPE_DCBL); HRPWM_setTripZoneDigitalCompareEventCondition(myEPWM1_BASE, EPWM_TZ_DC_OUTPUT_B1, EPWM_TZ_EVENT_DCXH_HIGH); HRPWM_setDigitalCompareEventSyncMode(myEPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_EVENT_INPUT_NOT_SYNCED); (myEPWM1_BASE, EPWM_DC_MODULE_B, EPWM_DC_EVENT_1, EPWM_DC_CBC_LATCH_ENABLED); HRPWM_enableAutoConversion(myEPWM1_BASE); HRPWM_setMEPEdgeSelect(myEPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE); HRPWM_setCounterCompareShadowLoadEvent(myEPWM1_BASE, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD); HRPWM_setMEPEdgeSelect(myEPWM1_BASE, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE); HRPWM_setCounterCompareShadowLoadEvent(myEPWM1_BASE, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD); HRPWM_enablePeriodControl(myEPWM1_BASE); HRPWM_setDeadbandMEPEdgeSelect(myEPWM1_BASE, HRPWM_DB_MEP_CTRL_RED_FED); HRPWM_setRisingEdgeDelayLoadMode(myEPWM1_BASE, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD); HRPWM_setFallingEdgeDelayLoadMode(myEPWM1_BASE, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD); HRPWM_setOutputSwapMode(myEPWM1_BASE, true); EPWM_setClockPrescaler(CLA_Clock_PWM_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1); EPWM_setPeriodLoadMode(CLA_Clock_PWM_BASE, EPWM_PERIOD_DIRECT_LOAD); EPWM_setTimeBasePeriod(CLA_Clock_PWM_BASE, 3750); EPWM_setTimeBaseCounter(CLA_Clock_PWM_BASE, 0); EPWM_setTimeBaseCounterMode(CLA_Clock_PWM_BASE, EPWM_COUNTER_MODE_UP); EPWM_disablePhaseShiftLoad(CLA_Clock_PWM_BASE); EPWM_setPhaseShift(CLA_Clock_PWM_BASE, 0); EPWM_setSyncInPulseSource(CLA_Clock_PWM_BASE, EPWM_SYNC_IN_PULSE_SRC_DISABLE); EPWM_setCounterCompareValue(CLA_Clock_PWM_BASE, EPWM_COUNTER_COMPARE_A, 0); EPWM_setCounterCompareShadowLoadMode(CLA_Clock_PWM_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setCounterCompareValue(CLA_Clock_PWM_BASE, EPWM_COUNTER_COMPARE_B, 0); EPWM_setCounterCompareShadowLoadMode(CLA_Clock_PWM_BASE, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); EPWM_setActionQualifierAction(CLA_Clock_PWM_BASE, EPWM_AQ_OUTPUT_B, EPWM_AQ_OUTPUT_NO_CHANGE, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); EPWM_setRisingEdgeDelayCountShadowLoadMode(CLA_Clock_PWM_BASE, EPWM_RED_LOAD_ON_CNTR_ZERO); EPWM_setFallingEdgeDelayCountShadowLoadMode(CLA_Clock_PWM_BASE, EPWM_FED_LOAD_ON_CNTR_ZERO); EPWM_disableRisingEdgeDelayCountShadowLoadMode(CLA_Clock_PWM_BASE); EPWM_disableFallingEdgeDelayCountShadowLoadMode(CLA_Clock_PWM_BASE); } //***************************************************************************** // // GPIO Configurations // //***************************************************************************** void GPIO_init(){ DIS_LLC_GPIO_init(); N_WINDOW_input_init(); P_WINDOW_input_init(); INRUSH_CNTRL_GPIO_init(); ENABLE_CAN_init(); DBA_STB_N_init(); DBA_CAN_ERROR_init(); HW_DISABLE_GPIO_init(); DISABLE_GPIO_init(); DIS_SR_CON_GPIO_init(); FAN_ON_GPIO_init(); DIS_PFC_GPIO_init(); GPIO6_DEBUG_init(); } void DIS_LLC_GPIO_init(){ GPIO_setPadConfig(DIS_LLC_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DIS_LLC_GPIO, GPIO_QUAL_SYNC); GPIO_setDirectionMode(DIS_LLC_GPIO, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(DIS_LLC_GPIO, GPIO_CORE_CPU1_CLA1); } void N_WINDOW_input_init(){ GPIO_setPadConfig(N_WINDOW_input, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(N_WINDOW_input, GPIO_QUAL_SYNC); GPIO_setDirectionMode(N_WINDOW_input, GPIO_DIR_MODE_IN); GPIO_setControllerCore(N_WINDOW_input, GPIO_CORE_CPU1); } void P_WINDOW_input_init(){ GPIO_setPadConfig(P_WINDOW_input, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(P_WINDOW_input, GPIO_QUAL_SYNC); GPIO_setDirectionMode(P_WINDOW_input, GPIO_DIR_MODE_IN); GPIO_setControllerCore(P_WINDOW_input, GPIO_CORE_CPU1); } void INRUSH_CNTRL_GPIO_init(){ GPIO_setPadConfig(INRUSH_CNTRL_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(INRUSH_CNTRL_GPIO, GPIO_QUAL_SYNC); GPIO_setDirectionMode(INRUSH_CNTRL_GPIO, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(INRUSH_CNTRL_GPIO, GPIO_CORE_CPU1_CLA1); } void ENABLE_CAN_init(){ GPIO_setPadConfig(ENABLE_CAN, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(ENABLE_CAN, GPIO_QUAL_SYNC); GPIO_setDirectionMode(ENABLE_CAN, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(ENABLE_CAN, GPIO_CORE_CPU1); } void DBA_STB_N_init(){ GPIO_writePin(DBA_STB_N, 0); GPIO_setPadConfig(DBA_STB_N, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DBA_STB_N, GPIO_QUAL_SYNC); GPIO_setDirectionMode(DBA_STB_N, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(DBA_STB_N, GPIO_CORE_CPU1); } void DBA_CAN_ERROR_init(){ GPIO_setPadConfig(DBA_CAN_ERROR, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DBA_CAN_ERROR, GPIO_QUAL_SYNC); GPIO_setDirectionMode(DBA_CAN_ERROR, GPIO_DIR_MODE_IN); GPIO_setControllerCore(DBA_CAN_ERROR, GPIO_CORE_CPU1); } void HW_DISABLE_GPIO_init(){ GPIO_setPadConfig(HW_DISABLE_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(HW_DISABLE_GPIO, GPIO_QUAL_SYNC); GPIO_setDirectionMode(HW_DISABLE_GPIO, GPIO_DIR_MODE_IN); GPIO_setControllerCore(HW_DISABLE_GPIO, GPIO_CORE_CPU1); } void DISABLE_GPIO_init(){ GPIO_setPadConfig(DISABLE_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DISABLE_GPIO, GPIO_QUAL_SYNC); GPIO_setDirectionMode(DISABLE_GPIO, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(DISABLE_GPIO, GPIO_CORE_CPU1_CLA1); } void DIS_SR_CON_GPIO_init(){ GPIO_setPadConfig(DIS_SR_CON_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DIS_SR_CON_GPIO, GPIO_QUAL_SYNC); GPIO_setDirectionMode(DIS_SR_CON_GPIO, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(DIS_SR_CON_GPIO, GPIO_CORE_CPU1_CLA1); } void FAN_ON_GPIO_init(){ GPIO_writePin(FAN_ON_GPIO, 1); GPIO_setPadConfig(FAN_ON_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(FAN_ON_GPIO, GPIO_QUAL_SYNC); GPIO_setDirectionMode(FAN_ON_GPIO, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(FAN_ON_GPIO, GPIO_CORE_CPU1); } void DIS_PFC_GPIO_init(){ GPIO_setPadConfig(DIS_PFC_GPIO, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(DIS_PFC_GPIO, GPIO_QUAL_SYNC); GPIO_setDirectionMode(DIS_PFC_GPIO, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(DIS_PFC_GPIO, GPIO_CORE_CPU1_CLA1); } void GPIO6_DEBUG_init(){ GPIO_writePin(GPIO6_DEBUG, 0); GPIO_setPadConfig(GPIO6_DEBUG, GPIO_PIN_TYPE_STD); GPIO_setQualificationMode(GPIO6_DEBUG, GPIO_QUAL_SYNC); GPIO_setDirectionMode(GPIO6_DEBUG, GPIO_DIR_MODE_OUT); GPIO_setControllerCore(GPIO6_DEBUG, GPIO_CORE_CPU1); } //***************************************************************************** // // INPUTXBAR Configurations // //***************************************************************************** void INPUTXBAR_init(){ myINPUTXBARINPUT0_init(); myINPUTXBARINPUT1_init(); } void myINPUTXBARINPUT0_init(){ XBAR_setInputPin(INPUTXBAR_BASE, myINPUTXBARINPUT0_INPUT, myINPUTXBARINPUT0_SOURCE); } void myINPUTXBARINPUT1_init(){ XBAR_setInputPin(INPUTXBAR_BASE, myINPUTXBARINPUT1_INPUT, myINPUTXBARINPUT1_SOURCE); } //***************************************************************************** // // MEMCFG Configurations // //***************************************************************************** void MEMCFG_init(){ // // Initialize RAMs // MemCfg_initSections(MEMCFG_SECT_MSGCPUTOCLA1); MemCfg_initSections(MEMCFG_SECT_MSGCLA1TOCPU); while(!MemCfg_getInitStatus(MEMCFG_SECT_MSGCPUTOCLA1)); while(!MemCfg_getInitStatus(MEMCFG_SECT_MSGCLA1TOCPU)); // // Configure LSRAMs // MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMCONTROLLER_CPU_CLA1); MemCfg_setCLAMemType(MEMCFG_SECT_LS0, MEMCFG_CLA_MEM_DATA); MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMCONTROLLER_CPU_CLA1); MemCfg_setCLAMemType(MEMCFG_SECT_LS1, MEMCFG_CLA_MEM_PROGRAM); MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS2, MEMCFG_LSRAMCONTROLLER_CPU_CLA1); MemCfg_setCLAMemType(MEMCFG_SECT_LS2, MEMCFG_CLA_MEM_PROGRAM); MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS3, MEMCFG_LSRAMCONTROLLER_CPU_CLA1); MemCfg_setCLAMemType(MEMCFG_SECT_LS3, MEMCFG_CLA_MEM_PROGRAM); MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS4, MEMCFG_LSRAMCONTROLLER_CPU_CLA1); MemCfg_setCLAMemType(MEMCFG_SECT_LS4, MEMCFG_CLA_MEM_PROGRAM); MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS5, MEMCFG_LSRAMCONTROLLER_CPU_CLA1); MemCfg_setCLAMemType(MEMCFG_SECT_LS5, MEMCFG_CLA_MEM_PROGRAM); MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS6, MEMCFG_LSRAMCONTROLLER_CPU_CLA1); MemCfg_setCLAMemType(MEMCFG_SECT_LS6, MEMCFG_CLA_MEM_PROGRAM); MemCfg_setLSRAMControllerSel(MEMCFG_SECT_LS7, MEMCFG_LSRAMCONTROLLER_CPU_ONLY); // // Configure GSRAMs // // // Configure Access Protection for RAMs // MemCfg_setProtection(MEMCFG_SECT_M0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_M1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS2, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS3, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS4, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS5, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS6, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_LS7, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE); MemCfg_setProtection(MEMCFG_SECT_GS0, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE | MEMCFG_PROT_ALLOWHICWRITE); MemCfg_setProtection(MEMCFG_SECT_GS1, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE | MEMCFG_PROT_ALLOWHICWRITE); MemCfg_setProtection(MEMCFG_SECT_GS2, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE | MEMCFG_PROT_ALLOWHICWRITE); MemCfg_setProtection(MEMCFG_SECT_GS3, MEMCFG_PROT_ALLOWCPUFETCH | MEMCFG_PROT_ALLOWCPUWRITE | MEMCFG_PROT_ALLOWDMAWRITE | MEMCFG_PROT_ALLOWHICWRITE); // // Lock/Commit Registers // // // Enable Access Violation Interrupt // // // Correctable error Interrupt // MemCfg_setCorrErrorThreshold(0); MemCfg_disableCorrErrorInterrupt(MEMCFG_CERR_CPUREAD); } //***************************************************************************** // // SCI Configurations // //***************************************************************************** void SCI_init(){ mySCI0_init(); } void mySCI0_init(){ SCI_clearInterruptStatus(mySCI0_BASE, SCI_INT_RXFF | SCI_INT_TXFF | SCI_INT_FE | SCI_INT_OE | SCI_INT_PE | SCI_INT_RXERR | SCI_INT_RXRDY_BRKDT | SCI_INT_TXRDY); SCI_clearOverflowStatus(mySCI0_BASE); SCI_resetTxFIFO(mySCI0_BASE); SCI_resetRxFIFO(mySCI0_BASE); SCI_resetChannels(mySCI0_BASE); SCI_setConfig(mySCI0_BASE, DEVICE_LSPCLK_FREQ, mySCI0_BAUDRATE, (SCI_CONFIG_WLEN_8|SCI_CONFIG_STOP_ONE|SCI_CONFIG_PAR_NONE)); SCI_disableLoopback(mySCI0_BASE); SCI_performSoftwareReset(mySCI0_BASE); SCI_setFIFOInterruptLevel(mySCI0_BASE, SCI_FIFO_TX0, SCI_FIFO_RX0); SCI_enableFIFO(mySCI0_BASE); SCI_enableModule(mySCI0_BASE); } //***************************************************************************** // // SYNC Scheme Configurations // //***************************************************************************** void SYNC_init(){ SysCtl_setSyncOutputConfig(SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT); // // SOCA // SysCtl_enableExtADCSOCSource(0); // // SOCB // SysCtl_enableExtADCSOCSource(0); }