#include "DSP2803x_Device.h" // DSP28 Headerfile Include File #include "DSP2803x_Examples.h" // DSP28 Examples Include File void initmaster(void) // Initialize eCAN-A module { struct ECAN_REGS ECanaShadow; EALLOW; GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA) GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA) GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation /// EDIS; /* Create a shadow register structure for the CAN control registers. This is needed, since only 32-bit access is allowed to these registers. 16-bit access to these registers could potentially corrupt the register contents or return false data. */ /// EALLOW; // EALLOW enables access to protected bits /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all; ECanaShadow.CANTIOC.bit.TXFUNC = 1; ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all; ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all; ECanaShadow.CANRIOC.bit.RXFUNC = 1; ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all; /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ // HECC mode also enables time-stamping feature ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.SCB = 1; ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; /* Initialize all bits of 'Message Control Register' to zero */ // Some bits of MSGCTRL register come up in an unknown state. For proper operation, // all bits (including reserved bits) of MSGCTRL must be initialized to zero ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000; ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000; // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again // as a matter of precaution. ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */ ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */ ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */ ECanaRegs.CANGIF1.all = 0xFFFFFFFF; /* Configure bit timing parameters for eCANA*/ ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; // Wait until the CPU has been granted permission to change the configuration registers do { ECanaShadow.CANES.all = ECanaRegs.CANES.all; } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set.. ECanaShadow.CANBTC.all = 0; /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps See Note at end of file. */ ECanaShadow.CANBTC.bit.BRPREG = 2; ECanaShadow.CANBTC.bit.TSEG2REG = 1; ECanaShadow.CANBTC.bit.TSEG1REG = 6; ECanaShadow.CANBTC.bit.SAM = 1; ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all; ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0 ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; // Wait until the CPU no longer has permission to change the configuration registers do { ECanaShadow.CANES.all = ECanaRegs.CANES.all; } while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared.. /* Disable all Mailboxes */ ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs /// EDIS; ECanaMboxes.MBOX0.MSGID.all = 0x80000000;//0x9555AAA0; ECanaMboxes.MBOX1.MSGID.all = 0x80000001;//0x9555AAA1; ECanaMboxes.MBOX2.MSGID.all = 0x80000002;//0x9555AAA2; ECanaMboxes.MBOX3.MSGID.all = 0x80000003;//0x9555AAA3; ECanaMboxes.MBOX4.MSGID.all = 0x80000004;//0x9555AAA4; ECanaMboxes.MBOX5.MSGID.all = 0x80000005;//0x9555AAA5; ECanaMboxes.MBOX6.MSGID.all = 0x80000006;//0x9555AAA6; ECanaMboxes.MBOX7.MSGID.all = 0x80000007;//0x9555AAA7; ECanaMboxes.MBOX8.MSGID.all = 0x80000008;//0x9555AAA8; ECanaMboxes.MBOX9.MSGID.all = 0x80000009;//0x9555AAA9; ECanaMboxes.MBOX10.MSGID.all = 0x8000000a;//0x9555AAAA; ECanaMboxes.MBOX11.MSGID.all = 0x8000000b;//0x9555AAAB; ECanaMboxes.MBOX12.MSGID.all = 0x8000000c;//0x9555AAAC; ECanaMboxes.MBOX13.MSGID.all = 0x8000000d;//0x9555AAAD; ECanaMboxes.MBOX14.MSGID.all = 0x8000000e;//0x9555AAAE; ECanaMboxes.MBOX15.MSGID.all = 0x8000000f;//0x9555AAAF; // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31 ECanaMboxes.MBOX16.MSGID.all = 0x81111110;//0x9555AAA0; ECanaMboxes.MBOX17.MSGID.all = 0x81111111;//0x9555AAA1; ECanaMboxes.MBOX18.MSGID.all = 0x81111112;//0x9555AAA2; ECanaMboxes.MBOX19.MSGID.all = 0x81111113;//0x9555AAA3; ECanaMboxes.MBOX20.MSGID.all = 0x81111114;//0x9555AAA4; ECanaMboxes.MBOX21.MSGID.all = 0x81111115;//0x9555AAA5; ECanaMboxes.MBOX22.MSGID.all = 0x81111116;//0x9555AAA6; ECanaMboxes.MBOX23.MSGID.all = 0x81111117;//0x9555AAA7; ECanaMboxes.MBOX24.MSGID.all = 0x81111118;//0x9555AAA8; ECanaMboxes.MBOX25.MSGID.all = 0x81111119;//0x9555AAA9; ECanaMboxes.MBOX26.MSGID.all = 0x8111111a;//0x9555AAAA; ECanaMboxes.MBOX27.MSGID.all = 0x8111111b;//0x9555AAAB; ECanaMboxes.MBOX28.MSGID.all = 0x8111111c;//0x9555AAAC; ECanaMboxes.MBOX29.MSGID.all = 0x8111111d;//0x9555AAAD; ECanaMboxes.MBOX30.MSGID.all = 0x8111111e;//0x9555AAAE; ECanaMboxes.MBOX31.MSGID.all = 0x8111111f;//0x9555AAAF; // Configure Mailboxes 0-15 as Tx, 16-31 as Rx // Since this write is to the entire register (instead of a bit // field) a shadow register is not required. ECanaRegs.CANMD.all = 0xFFFF0000; // Enable all Mailboxes */ // Since this write is to the entire register (instead of a bit // field) a shadow register is not required. ECanaRegs.CANME.all = 0xFFFFFFFF; // Specify that 8 bits will be sent/received ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 4;//8; ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 4;//8; // Write to the mailbox RAM field of MBOX0 - 15 ECanaMboxes.MBOX0.MDL.all = 0x12345678; ECanaMboxes.MBOX0.MDH.all = 0x13579ace; ECanaMboxes.MBOX1.MDL.all = 0x11111111; ECanaMboxes.MBOX1.MDH.all = 0x11111111; ECanaMboxes.MBOX2.MDL.all = 0x22222222; ECanaMboxes.MBOX2.MDH.all = 0x22222222; ECanaMboxes.MBOX3.MDL.all = 0x33333333; ECanaMboxes.MBOX3.MDH.all = 0x33333333; ECanaMboxes.MBOX4.MDL.all = 0x44444444; ECanaMboxes.MBOX4.MDH.all = 0x44444444; ECanaMboxes.MBOX5.MDL.all = 0x55555555; ECanaMboxes.MBOX5.MDH.all = 0x55555555; ECanaMboxes.MBOX6.MDL.all = 0x66666666; ECanaMboxes.MBOX6.MDH.all = 0x66666666; ECanaMboxes.MBOX7.MDL.all = 0x77777777; ECanaMboxes.MBOX7.MDH.all = 0x77777777; ECanaMboxes.MBOX8.MDL.all = 0x88888888; ECanaMboxes.MBOX8.MDH.all = 0x88888888; ECanaMboxes.MBOX9.MDL.all = 0x99999999; ECanaMboxes.MBOX9.MDH.all = 0x99999999; ECanaMboxes.MBOX10.MDL.all = 0xaaaaaaaa; ECanaMboxes.MBOX10.MDH.all = 0xaaaaaaaa; ECanaMboxes.MBOX11.MDL.all = 0xbbbbbbbb; ECanaMboxes.MBOX11.MDH.all = 0xbbbbbbbb; ECanaMboxes.MBOX12.MDL.all = 0xcccccccc; ECanaMboxes.MBOX12.MDH.all = 0xcccccccc; ECanaMboxes.MBOX13.MDL.all = 0xdddddddd; ECanaMboxes.MBOX13.MDH.all = 0xdddddddd; ECanaMboxes.MBOX14.MDL.all = 0xeeeeeeee; ECanaMboxes.MBOX14.MDH.all = 0xeeeeeeee; ECanaMboxes.MBOX15.MDL.all = 0xffffffff; ECanaMboxes.MBOX15.MDH.all = 0xffffffff; // Since this write is to the entire register (instead of a bit // field) a shadow register is not required. /// EALLOW; /// ECanaRegs.CANMIM.all = 0xFFFFFFFF; // Configure the eCAN for self test mode // Enable the enhanced features of the eCAN. /// EALLOW; /// ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; /// ECanaShadow.CANMC.bit.STM = 1; // Configure CAN for self-test mode /// ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; /// EDIS; }