MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   //RAMLS0          	: origin = 0x008000, length = 0x000800
   //RAMLS1          	: origin = 0x008800, length = 0x000800
   //RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS_COMBINED : origin = 0x00008000, length = 0x00001800  /* total 8 KB from LS0–LS2 */
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */

   /* Z1 OTP.  LinkPointers */
   DCSM_OTP_Z1_LINKPOINTER   : origin = 0x78000, length = 0x00000C
   /* Z1 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z1_GPREG         : origin = 0x7800C, length = 0x000004
   /* Z1 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z1_PSWDLOCK	    : origin = 0x78010, length = 0x000004
   /* Z1 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z1_CRCLOCK	    : origin = 0x78014, length = 0x000004
   /* Z1 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z1_JTAGLOCK	    : origin = 0x78018, length = 0x000004
   /* Z1 OTP.  RESERVED/BOOTCTRL */
   DCSM_OTP_Z1_BOOTCTRL	    : origin = 0x7801C, length = 0x000004

   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
   /* Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
   DCSM_ZSEL_Z1_P0	        : origin = 0x78020, length = 0x000010

   /* Z2 OTP.  LinkPointers */
   DCSM_OTP_Z2_LINKPOINTER	: origin = 0x78200, length = 0x00000C
   /* Z2 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z2_GPREG	        : origin = 0x7820C, length = 0x000004
   /* Z2 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z2_PSWDLOCK	    : origin = 0x78210, length = 0x000004
   /* Z2 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z2_CRCLOCK	    : origin = 0x78214, length = 0x000004
   /* Z2 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z2_JTAGLOCK	    : origin = 0x78218, length = 0x000004
   /* Z2 OTP.  GPREG3/BOOTCTRL */
   DCSM_OTP_Z2_BOOTCTRL	    : origin = 0x7821C, length = 0x000004

   /* DCSM Z2 Zone Select Contents (!!Movable!!) */
   /* Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
   DCSM_ZSEL_Z2_P0	        : origin = 0x78220, length = 0x000010

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   EPWM1:		origin = 0x004000, length = 0x000100    /* epwm1 registers */
   EPWM2:		origin = 0x004100, length = 0x000100    /* epwm1 registers */
   EPWM3:		origin = 0x004200, length = 0x000100    /* epwm1 registers */
   CAP1:		origin = 0x005000, length = 0x000020    /* ecap1 registers */

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WD_REG         : origin = 0x00007000, length = 0x0000003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF     PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1

   /* Initialized sections in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initialized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

	/*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/
   /* Section for RAM functions */
   /* This section will be used by functions marked with __attribute__((ramfunc)) */
   .TI.ramfunc         : {}
                         LOAD = FLASHD,
                         RUN = RAMLS_COMBINED,
                         LOAD_START(RamfuncsLoadStart),
                         LOAD_SIZE(RamfuncsLoadSize),
                         LOAD_END(RamfuncsLoadEnd),
                         RUN_START(RamfuncsRunStart),
                         RUN_SIZE(RamfuncsRunSize),
                         RUN_END(RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)

   /* The following sections are for shared memory between CPU1 and CPU2 */
   GROUP : > CPU1TOCPU2RAM, PAGE = 1
   {
       PUTBUFFER
       PUTWRITEIDX
       GETREADIDX
   }

   GROUP : > CPU2TOCPU1RAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }

   GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   GpioDataRegsFile:	load = GPIODAT      PAGE = 1

   ePWM1RegsFile:	load = EPWM1		PAGE = 1
   ePWM2RegsFile:	load = EPWM2		PAGE = 1
   ePWM3RegsFile:	load = EPWM3		PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   IpcRegsFile:		load = IpcRegs      PAGE = 1
   PieVectRegsFile:		load = PieVectRegs      PAGE = 1
   PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   SHARERAMGS0:		load = RAMGS0      PAGE = 1
   SHARERAMGS1:		load = RAMGS1      PAGE = 1
   SHARERAMGS2:		load = RAMGS2      PAGE = 1

   WdRegsFile:		load = WD_REG      PAGE = 1

	dcsm_otp_z1_linkpointer 	: > DCSM_OTP_Z1_LINKPOINTER		PAGE = 0
   dcsm_otp_z1_pswdlock		: > DCSM_OTP_Z1_PSWDLOCK		PAGE = 0
   dcsm_otp_z1_crclock		: > DCSM_OTP_Z1_CRCLOCK			PAGE = 0
    dcsm_otp_z1_jtaglock    : > DCSM_OTP_Z1_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z1_bootctrl		: > DCSM_OTP_Z1_BOOTCTRL		PAGE = 0
   dcsm_zsel_z1				: > DCSM_ZSEL_Z1_P0				PAGE = 0

   dcsm_otp_z2_linkpointer	: > DCSM_OTP_Z2_LINKPOINTER		PAGE = 0
   dcsm_otp_z2_pswdlock		: > DCSM_OTP_Z2_PSWDLOCK		PAGE = 0
   dcsm_otp_z2_crclock		: > DCSM_OTP_Z2_CRCLOCK			PAGE = 0
    dcsm_otp_z2_jtaglock    : > DCSM_OTP_Z2_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z2_bootctrl		: > DCSM_OTP_Z2_BOOTCTRL		PAGE = 0, type = DSECT
   dcsm_zsel_z2				: > DCSM_ZSEL_Z2_P0				PAGE = 0

   /* Debugging symbols for CPU1 */
   /*.debug_CPU1         : > RAMM0,       PAGE = 1
   .debug_data         : > RAMD0,       PAGE = 1*/
}