#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
void initboth11(void);
void main(void)
{

   struct ECAN_REGS ECanaShadow;
   InitSysCtrl();

    EALLOW;
    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;     // Enable pull-up for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;     // Enable pull-up for GPIO31 (CANTXA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;    // Configure GPIO30 for CANRXA operation
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;    // Configure GPIO31 for CANTXA operation
//    EDIS;
 
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();
	initboth11(); // Initialize eCAN-A module
    EALLOW;
    // Mailboxs can be written to 16-bits or 32-bits at a time
    // Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15
    ECanaMboxes.MBOX0.MSGID.all = 0x80000000;
    ECanaMboxes.MBOX1.MSGID.all = 0x80000001;
    ECanaMboxes.MBOX2.MSGID.all = 0x80000002;
    ECanaMboxes.MBOX3.MSGID.all = 0x80000003;
    ECanaMboxes.MBOX4.MSGID.all = 0x80000004;
    ECanaMboxes.MBOX5.MSGID.all = 0x80000005;
    ECanaMboxes.MBOX6.MSGID.all = 0x80000006;
    ECanaMboxes.MBOX7.MSGID.all = 0x80000007;
    ECanaMboxes.MBOX8.MSGID.all = 0x80000008;
    ECanaMboxes.MBOX9.MSGID.all = 0x80000009;
    ECanaMboxes.MBOX10.MSGID.all = 0x8000000A;
    ECanaMboxes.MBOX11.MSGID.all = 0x8000000B;
    ECanaMboxes.MBOX12.MSGID.all = 0x8000000C;
    ECanaMboxes.MBOX13.MSGID.all = 0x8000000D;
    ECanaMboxes.MBOX14.MSGID.all = 0x8000000E;
    ECanaMboxes.MBOX15.MSGID.all = 0x8000000F;

    // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
    ECanaMboxes.MBOX16.MSGID.all = 0x81111110;
    ECanaMboxes.MBOX17.MSGID.all = 0x81111111;
    ECanaMboxes.MBOX18.MSGID.all = 0x81111112;
    ECanaMboxes.MBOX19.MSGID.all = 0x81111113;
    ECanaMboxes.MBOX20.MSGID.all = 0x81111114;
    ECanaMboxes.MBOX21.MSGID.all = 0x81111115;
    ECanaMboxes.MBOX22.MSGID.all = 0x81111116;
    ECanaMboxes.MBOX23.MSGID.all = 0x81111117;
    ECanaMboxes.MBOX24.MSGID.all = 0x81111118;
    ECanaMboxes.MBOX25.MSGID.all = 0x81111119;
    ECanaMboxes.MBOX26.MSGID.all = 0x8111111A;
    ECanaMboxes.MBOX27.MSGID.all = 0x8111111B;
    ECanaMboxes.MBOX28.MSGID.all = 0x8111111C;
    ECanaMboxes.MBOX29.MSGID.all = 0x8111111D;
    ECanaMboxes.MBOX30.MSGID.all = 0x8111111E;
    ECanaMboxes.MBOX31.MSGID.all = 0x8111111F;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANMD.all = 0xFFFF0000;

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANME.all = 0xFFFFFFFF;

    // Specify that 8 bits will be sent/received
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;

    // Write to the mailbox RAM field of MBOX0 - 15
    ECanaMboxes.MBOX0.MDL.all = 0x12345678;
    ECanaMboxes.MBOX0.MDH.all = 0x13579ace;

    ECanaMboxes.MBOX1.MDL.all = 0x11111111;
    ECanaMboxes.MBOX1.MDH.all = 0x11111111;

    ECanaMboxes.MBOX2.MDL.all = 0x22222222;
    ECanaMboxes.MBOX2.MDH.all = 0x22222222;

    ECanaMboxes.MBOX3.MDL.all = 0x33333333;
    ECanaMboxes.MBOX3.MDH.all = 0x33333333;

    ECanaMboxes.MBOX4.MDL.all = 0x44444444;
    ECanaMboxes.MBOX4.MDH.all = 0x44444444;

    ECanaMboxes.MBOX5.MDL.all = 0x55555555;
    ECanaMboxes.MBOX5.MDH.all = 0x55555555;

    ECanaMboxes.MBOX6.MDL.all = 0x66666666;
    ECanaMboxes.MBOX6.MDH.all = 0x66666666;

    ECanaMboxes.MBOX7.MDL.all = 0x77777777;
    ECanaMboxes.MBOX7.MDH.all = 0x77777777;

    ECanaMboxes.MBOX8.MDL.all = 0x88888888;
    ECanaMboxes.MBOX8.MDH.all = 0x88888888;

    ECanaMboxes.MBOX9.MDL.all = 0x99999999;
    ECanaMboxes.MBOX9.MDH.all = 0x99999999;

    ECanaMboxes.MBOX10.MDL.all = 0xaaaaaaaa;
    ECanaMboxes.MBOX10.MDH.all = 0xaaaaaaaa;

    ECanaMboxes.MBOX11.MDL.all = 0xbbbbbbbb;
    ECanaMboxes.MBOX11.MDH.all = 0xbbbbbbbb;

    ECanaMboxes.MBOX12.MDL.all = 0xcccccccc;
    ECanaMboxes.MBOX12.MDH.all = 0xcccccccc;

    ECanaMboxes.MBOX13.MDL.all = 0xdddddddd;
    ECanaMboxes.MBOX13.MDH.all = 0xdddddddd;

    ECanaMboxes.MBOX14.MDL.all = 0xeeeeeeee;
    ECanaMboxes.MBOX14.MDH.all = 0xeeeeeeee;

    ECanaMboxes.MBOX15.MDL.all = 0xffffffff;
    ECanaMboxes.MBOX15.MDH.all = 0xffffffff;

    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
///    EALLOW;
///    ECanaRegs.CANMIM.all = 0xFFFFFFFF;

    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.
///    EALLOW;
///    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
///    ECanaShadow.CANMC.bit.STM = 1;    // Configure CAN for self-test mode
///    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
///    EDIS;

    // Begin transmitting
    for(;;)
    {
//	   ECanaRegs.CANTRR.all=0x0000ffff;
//       while(ECanaRegs.CANTRS.all != 0x00000000 ) {} 
//EALLOW;
       ECanaRegs.CANTRS.all = 0x0000FFFF;  // Set TRS for all transmit mailboxes
       while(ECanaRegs.CANTA.all != 0x0000ffff ) {}  // Wait for all TAn bits to be set..
       ECanaRegs.CANTA.all = 0x0000FFFF;   // Clear all TAn
    }
}