/*
 * main.c
 */
#include "F2837xS_device.h"
#include "F28x_Project.h"
#include "pinmux.h"

static void InitPWM(void);
static void InitCMPSS1(void);

int main(void)
{
   InitSysCtrl();
   GPIO_setPinMuxConfig();
   InitPWM();

   /* Output the CMPSS output to GPIO17. */
   EALLOW;
   OutputXbarRegs.OUTPUT8MUX0TO15CFG.bit.MUX0 = 1;
   OutputXbarRegs.OUTPUT8MUXENABLE.bit.MUX0 = 1;
   EDIS;

   InitCMPSS1();

   /* Generate a 500Hz 50% PWM signal. */
   EPwm2Regs.TBPRD = 49999;
   EPwm2Regs.CMPA.bit.CMPA = 0;
   EPwm2Regs.CMPB.bit.CMPB = 25000;
   EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
   EPwm2Regs.AQCTLA.bit.CBU = AQ_CLEAR;
   EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

   EALLOW;
   EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 1;
   EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;

   EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0xF; // select trip combination input (DCBHTRIPSEL register)
   EPwm2Regs.TZDCSEL.bit.DCBEVT2 = TZ_DCBH_HI;
   EPwm2Regs.TZSEL.bit.DCBEVT2 = 1;
   EPwm2Regs.DCBHTRIPSEL.bit.TRIPINPUT4 = 1;
   EDIS;

   while (1)
      ;
}

static void InitPWM()
{
   EALLOW;
   EPwm2Regs.TBPRD = 0xFFFF;
   EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;           // Phase is 0
   EPwm2Regs.TBCTR = 0x0000;                     // Clear counter

   /* Setup TBCLK. */
   EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
   EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
   /* Select division by 2*2. So TBCLK = 100MHz/4 = 25MHz. */
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;
   EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   /* Setup compare. */
   EPwm2Regs.CMPA.bit.CMPA = 0;
   EPwm2Regs.CMPB.bit.CMPB = 0;

   /* Action qualifier module uses shadow registers. */
   EPwm2Regs.AQCTL.bit.SHDWAQAMODE = 1;
   EPwm2Regs.AQCTL.bit.SHDWAQBMODE = 1;
   /* Set actions. */
   EPwm2Regs.AQCTLA.bit.CAU = AQ_NO_ACTION;
   EPwm2Regs.AQCTLA.bit.CBU = AQ_NO_ACTION;

   EPwm2Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
   EPwm2Regs.AQCTLB.bit.CBU = AQ_NO_ACTION;

   /* Activate deadband shadow register load at counter = 0. */
   EPwm2Regs.DBCTL2.bit.SHDWDBCTLMODE = 1;
   /* Active High complementary PWMs - setup the deadband. */
   EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
   /* Always invert ePWMB output. */
   EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
   EPwm2Regs.DBRED.bit.DBRED = 0;
   EPwm2Regs.DBFED.bit.DBFED = 0;

   EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
   EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
   EDIS;
}

static void InitCMPSS1()
{
   EALLOW;
   Cmpss1Regs.COMPSTSCLR.bit.HSYNCCLREN = 1;
   Cmpss1Regs.COMPSTSCLR.bit.LSYNCCLREN = 1;
   /* Lower threshold comparator must be inverted. */
   Cmpss1Regs.COMPCTL.bit.COMPLINV = 1;
   Cmpss1Regs.DACHVALS.all = 2048;
   Cmpss1Regs.DACLVALS.all = 1024;
   Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
   /* DAC needs some time for powering up. */
   DELAY_US(20);
   Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 4;
   Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 3;
   Cmpss1Regs.CTRIPLFILCTL.bit.SAMPWIN = 4;
   Cmpss1Regs.CTRIPLFILCTL.bit.THRESH = 3;
   Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;
   Cmpss1Regs.CTRIPLFILCTL.bit.FILINIT = 1;

   Cmpss1Regs.COMPSTSCLR.bit.HLATCHCLR = 1;
   Cmpss1Regs.COMPSTSCLR.bit.LLATCHCLR = 1;

   Cmpss1Regs.COMPCTL.bit.ASYNCHEN = 1;
   Cmpss1Regs.COMPCTL.bit.ASYNCLEN = 1;
   Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = 3;
   Cmpss1Regs.COMPCTL.bit.CTRIPLSEL = 3;
   Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = 3;
   Cmpss1Regs.COMPCTL.bit.CTRIPOUTLSEL = 3;
   EDIS;
}