#include "DSP28x_Project.h" // Device Headerfile and Examples Include File void main(void) { Uint16 j; struct ECAN_REGS ECanaShadow; InitSysCtrl(); { EALLOW; GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA) GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA) GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation EDIS; } DINT; InitPieCtrl(); IER = 0x0000; IFR = 0x0000; InitPieVectTable(); caninit(); // Initialize eCAN-A module // Write to the mailbox RAM field of MBOX0 - 15 ECanaMboxes.MBOX0.MDL.all = 0x12345678; ECanaMboxes.MBOX0.MDH.all = 0x13579ace; ECanaMboxes.MBOX1.MDL.all = 0x11111111; ECanaMboxes.MBOX1.MDH.all = 0x11111111; ECanaMboxes.MBOX2.MDL.all = 0x22222222; ECanaMboxes.MBOX2.MDH.all = 0x22222222; ECanaMboxes.MBOX3.MDL.all = 0x33333333; ECanaMboxes.MBOX3.MDH.all = 0x33333333; ECanaMboxes.MBOX4.MDL.all = 0x44444444; ECanaMboxes.MBOX4.MDH.all = 0x44444444; ECanaMboxes.MBOX5.MDL.all = 0x55555555; ECanaMboxes.MBOX5.MDH.all = 0x55555555; ECanaMboxes.MBOX6.MDL.all = 0x66666666; ECanaMboxes.MBOX6.MDH.all = 0x66666666; ECanaMboxes.MBOX7.MDL.all = 0x77777777; ECanaMboxes.MBOX7.MDH.all = 0x77777777; ECanaMboxes.MBOX8.MDL.all = 0x88888888; ECanaMboxes.MBOX8.MDH.all = 0x88888888; ECanaMboxes.MBOX9.MDL.all = 0x99999999; ECanaMboxes.MBOX9.MDH.all = 0x99999999; ECanaMboxes.MBOX10.MDL.all = 0xaaaaaaaa; ECanaMboxes.MBOX10.MDH.all = 0xaaaaaaaa; ECanaMboxes.MBOX11.MDL.all = 0xbbbbbbbb; ECanaMboxes.MBOX11.MDH.all = 0xbbbbbbbb; ECanaMboxes.MBOX12.MDL.all = 0xcccccccc; ECanaMboxes.MBOX12.MDH.all = 0xcccccccc; ECanaMboxes.MBOX13.MDL.all = 0xdddddddd; ECanaMboxes.MBOX13.MDH.all = 0xdddddddd; ECanaMboxes.MBOX14.MDL.all = 0xeeeeeeee; ECanaMboxes.MBOX14.MDH.all = 0xeeeeeeee; ECanaMboxes.MBOX15.MDL.all = 0xffffffff; ECanaMboxes.MBOX15.MDH.all = 0xffffffff; // Since this write is to the entire register (instead of a bit // field) a shadow register is not required. /// EALLOW; /// ECanaRegs.CANMIM.all = 0xFFFFFFFF; // Configure the eCAN for self test mode // Enable the enhanced features of the eCAN. /// EALLOW; /// ECanaShadow.CANMC.all = ECanaRegs.CANMC.all; /// ECanaShadow.CANMC.bit.STM = 1; // Configure CAN for self-test mode /// ECanaRegs.CANMC.all = ECanaShadow.CANMC.all; /// EDIS; // Begin transmitting for(;;) { ECanaRegs.CANTRS.all = 0x0000FFFF; // Set TRS for all transmit mailboxes while(ECanaRegs.CANTA.all != 0x0000FFFF ) {} // Wait for all TAn bits to be set.. ECanaRegs.CANTA.all = 0x0000FFFF; // Clear all TAn while(ECanaRegs.CANTA.all != 0x00000000 ) {} } } //=========================================================================== // No more. //===========================================================================