MEMORY {

/*
*********************************************************************************************************
*                                           -| MEMORY REGIONS
*											  -| FLASH Mode
*********************************************************************************************************
*/
	PAGE 0:
		RAMM0           	: origin = 0x000122, length = 0x0002DE
  		RAMD0           	: origin = 0x00B000, length = 0x000800
   		RAMLS0          	: origin = 0x008000, length = 0x000800



		BEGIN           	: origin = 0x080000, length = 0x000002
		FLASHA           	: origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   		FLASHB_H           	: origin = 0x082000, length = 0x026000	/* on-chip Flash */
		FLASHI				: origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
		FLASHJ				: origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
		FLASHK				: origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
		FLASHL				: origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
		FLASHM				: origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
		FLASHN				: origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

        CSM_RSVD   			: origin = 0x33FF80, length = 0x000076

        CSM_PWL    			: origin = 0x33FFF8, length = 0x000008
        ADC_CAL    			: origin = 0x380080, length = 0x000009

        BOOTROM    			: origin = 0x3FF27C, length = 0x000D44
        VECTORS    			: origin = 0x3FFFC0, length = 0x000040

	 PAGE 1:

		BOOT_RSVD	    	: origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   		RAMLS1          	: origin = 0x008800, length = 0x000800
		RAMM1				: origin = 0x000400, length = 0x000400
   		RAMLS_STACK      	: origin = 0x009000, length = 0x001800		/* LS2, LS3, LS4 */
		RAMD1				: origin = 0x00B800, length = 0x000800

		RAMLS5				: origin = 0x00A800, length = 0x000800

		RAMGS_BIG			: origin = 0x00C000, length = 0x010000		/* multiple RAM blocks in one definition, so a structure may be allocated crossing the boundaries */


		CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
		CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}

SECTIONS
{

/*
*********************************************************************************************************
*                                           -| LINKER SECTIONS
*											  -| FLASH Mode
*********************************************************************************************************
*/

//wrapper allignment for ram_start initialiser for OS
	ram_start  			: > BEGIN,           PAGE = 0, ALIGN(4)
	codestart           : > FLASHA       PAGE = 0, ALIGN(4)

    ramfuncs            :	LOAD = FLASHA,
                         	RUN = RAMLS0,
                         	LOAD_START(_RamfuncsLoadStart),
                         	LOAD_SIZE(_RamfuncsLoadSize),
                         	LOAD_END(_RamfuncsLoadEnd),
                         	RUN_START(_RamfuncsRunStart),
                         	RUN_SIZE(_RamfuncsRunSize),
                         	RUN_END(_RamfuncsRunEnd),
							PAGE = 0, ALIGN(4)

    .text      			: >> FLASHB_H,         	PAGE = 0, ALIGN(4)
    .cinit     			: > FLASHB_H,          	PAGE = 0, ALIGN(4)
    .pinit     			: > FLASHB_H,          	PAGE = 0, ALIGN(4)
    .switch    			: > FLASHB_H,          	PAGE = 0, ALIGN(4)
    .econst    			: > FLASHB_H,          	PAGE = 0, ALIGN(4)                                                           /* Default reset handler. Not used.                     */
    .reset     			: > VECTORS,         	PAGE = 0, TYPE = DSECT

    pie_vram   			: > RAMLS1,        	PAGE = 1

    .stack     			: > RAMM1,           PAGE = 1
    .ebss      			: > RAMGS_BIG,      PAGE = 1
    .esysmem   			: > RAMGS_BIG,       PAGE = 1
    task_stack			: > RAMLS_STACK, 	 PAGE = 1
    dma_region			: > CPU1TOCPU2RAM,	 PAGE = 1

	.switch             : > FLASHB_H,     PAGE = 0, ALIGN(4)


                                                                /* 128-bit CSM Password. Not used.                      */
	csm_rsvd   			: > CSM_RSVD,        PAGE = 0, TYPE = DSECT
	csmpasswds 			: > CSM_PWL,         PAGE = 0, TYPE = DSECT
                                                                /* ADC Calibration.                                     */
	.adc_cal   			: load = ADC_CAL,    PAGE = 0, TYPE = NOLOAD



	GROUP : > CPU1TOCPU2RAM, PAGE = 1
	{
		PUTBUFFER
		PUTWRITEIDX
		GETREADIDX
	}

	GROUP : > CPU2TOCPU1RAM, PAGE = 1
	{
		GETBUFFER
		GETWRITEIDX
		PUTREADIDX
	}
}