/*
//###########################################################################
// FILE:    F28M36x_generic_wshared_M3_RAM.cmd
// TITLE:   Linker Command File For F28M36x examples that run out of RAM
//          This does not include flash or OTP.
//          Keep in mind that C0 and C1 are protected by the code
//          security module.
//          What this means is in most cases you will want to move to
//          another memory map file which has more memory defined.
//###########################################################################
// $TI Release: F28M36x Support Library v207 $
// $Release Date: Mon Sep 21 16:44:39 CDT 2015 $
// $Copyright: Copyright (C) 2012-2015 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*/

--retain=g_pfnVectors

/* The following command line options are set as part of the CCS project.    */
/* If you are building using the command line, or for some reason want to    */
/* define them here, you can uncomment and modify these lines as needed.     */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone.              */
/*                                                                           */
/* --heap_size=0                                                             */
/* --stack_size=256                                                          */
/* --library=rtsv7M3_T_le_eabi.lib                                           */


/* System memory map */

MEMORY
{
    C0 (RWX)         : origin = 0x20000000, length = 0x2000
    C1 (RWX)         : origin = 0x20002000, length = 0x2000
    BOOT_RSVD (RX)   : origin = 0x20004000, length = 0x0FF8
    RESETISR (RWX)   : origin = 0x20004FF8, length = 0x0008
    INTVECS (RWX)    : origin = 0x20005000, length = 0x0258
    C2 (RWX)         : origin = 0x20005258, length = 0x0DA8
    C3 (RWX)         : origin = 0x20006000, length = 0x2000
    S0 (RWX)         : origin = 0x20008000, length = 0x2000
    S1 (RWX)         : origin = 0x2000A000, length = 0x2000
    S2 (RWX)         : origin = 0x2000C000, length = 0x2000
    S3 (RWX)         : origin = 0x2000E000, length = 0x2000
    S4 (RWX)         : origin = 0x20010000, length = 0x2000
    S5 (RWX)         : origin = 0x20012000, length = 0x2000
    S6 (RWX)         : origin = 0x20014000, length = 0x2000
    S7 (RWX)         : origin = 0x20016000, length = 0x2000
    
    C4  (RWX)        : origin = 0x20018000, length = 0x2000
    C5  (RWX)        : origin = 0x2001A000, length = 0x2000
    C6  (RWX)        : origin = 0x2001C000, length = 0x2000
    C7  (RWX)        : origin = 0x2001E000, length = 0x2000
    C8  (RWX)        : origin = 0x20020000, length = 0x2000
    C9  (RWX)        : origin = 0x20022000, length = 0x2000
    C10 (RWX)        : origin = 0x20024000, length = 0x2000
    C11 (RWX)        : origin = 0x20026000, length = 0x2000
    C12 (RWX)        : origin = 0x20028000, length = 0x2000
    C13 (RWX)        : origin = 0x2002A000, length = 0x2000
    C14 (RWX)        : origin = 0x2002C000, length = 0x2000
    C15 (RWX)        : origin = 0x2002E000, length = 0x2000
    
    CTOMRAM1 (RX)    : origin = 0x2007F000, length = 0x0100
    CTOMRAM2 (RX)	 : origin = 0x2007F100, length = 0x0100
    CTOMRAM3 (RX)	 : origin = 0x2007F200, length = 0x0100
    CTOMRAM4 (RX)	 : origin = 0x2007F300, length = 0x0100
    CTOMRAM5 (RX)	 : origin = 0x2007F400, length = 0x0100
    CTOMRAM6 (RX)	 : origin = 0x2007F500, length = 0x0100
    CTOMRAM7 (RX)	 : origin = 0x2007F600, length = 0x0100
    CTOMRAM8 (RX)	 : origin = 0x2007F700, length = 0x0100
    MTOCRAM1 (RWX)   : origin = 0x2007F800, length = 0x0100
    MTOCRAM2 (RWX)   : origin = 0x2007F900, length = 0x0100
    MTOCRAM3 (RWX)   : origin = 0x2007FA00, length = 0x0100
    MTOCRAM4 (RWX)   : origin = 0x2007FB00, length = 0x0100
    MTOCRAM5 (RWX)   : origin = 0x2007FC00, length = 0x0100
    MTOCRAM6 (RWX)   : origin = 0x2007FD00, length = 0x0100
    MTOCRAM7 (RWX)   : origin = 0x2007FE00, length = 0x0100
    MTOCRAM8 (RWX)   : origin = 0x2007FF00, length = 0x0100
	
	OTPSECLOCK       : origin = 0x00681000, length = 0x0004
    OTP_Reserved1    : origin = 0x00681004, length = 0x0004
    OTP_Reserved2    : origin = 0x00681008, length = 0x0004
    OTP_Z2_FLASH_START_ADDR             : origin = 0x0068100C, length = 0x0004
    OTP_EMACID       : origin = 0x00681010, length = 0x0008
    OTP_Reserved3    : origin = 0x00681018, length = 0x0004
    CUSTOMER_OTP_MAIN_OSC_CLK_FREQ      : origin = 0x0068101C, length = 0x0004
    OTP_Reserved4    : origin = 0x00681020, length = 0x0004
    OTP_BOOT_MODE_GPIO_CONFIGURE        : origin = 0x00681024, length = 0x0004
    OTP_Reserved5    : origin = 0x00681028, length = 0x0004
    OTP_ENTRY_POINT  : origin = 0x0068102C, length = 0x0004
    OTP_Reserved6    : origin = 0x00681030, length = 0x0010
}

/* Section allocation in memory */

SECTIONS
{
    .intvecs:   > INTVECS
    .resetisr:  > RESETISR
    .text   :   >> C0 | C1 | C2 | C3 | C4, crc_table(AppCrc, algorithm=CRC32_PRIME)
    .const  :   >> C0 | C1 | C2 | C3 | C4, crc_table(AppCrc, algorithm=CRC32_PRIME)
    .cinit  :   >  C0 | C1 | C2 | C3 | C4, crc_table(AppCrc, algorithm=CRC32_PRIME)
    .pinit  :   >> C0 | C1 | C2 | C3 | C4, crc_table(AppCrc, algorithm=CRC32_PRIME)
    .init_array :  > C0 | C1 | C2 | C3 | C4

    .vtable :   >> C0 | C1 | C2 | C3
    .data   :   >> C2 | C3 | C0 | C1 
    .bss    :   >> C2 | C3 | C0 | C1 
    .sysmem :   >  C0 | C1 | C2 | C3
    .stack  :   >  C0 | C1 | C2 | C3

    .TI.crctab : > C3  
    
    SHARERAMS0  : > S0
    SHARERAMS1  : > S1
    SHARERAMS2  : > S2
    SHARERAMS3  : > S3
    SHARERAMS4  : > S4
    SHARERAMS5  : > S5
    SHARERAMS6  : > S6
    SHARERAMS7  : > S7

   //AS: Added because the F28M36H33B22 does not have shared ram (S0 - S7).
   // This is utelizing the IPC MTOC and CTOM ram as shared ram
   MTOCSHARED          				: > MTOCRAM1
   MTOCSHARED_HANDCONTROLLER 		: > MTOCRAM2
   MTOCSHARED_MOTORCONTROLLER 		: > MTOCRAM3
   MTOCSHARED_LINACTUATOR			: > MTOCRAM4
   CTOMSHARED          				: > CTOMRAM1, TYPE = NOINIT
   CTOMSHARED_HANDCONTROLLER 		: > CTOMRAM2, TYPE = NOINIT
   CTOMSHARED_MOTORCONTROLLER 		: > CTOMRAM3, TYPE = NOINIT
   CTOMSHARED_LINACTUATOR			: > CTOMRAM4, TYPE = NOINIT

#ifdef __TI_COMPILER_VERSION
   #if __TI_COMPILER_VERSION >= 15009000
    .TI.ramfunc : {} > C0 | C1
   #endif
#endif
    
//    GROUP : > MTOCRAM
//    {
//        PUTBUFFER
//        PUTWRITEIDX
//        GETREADIDX
//    }

//    GROUP : > CTOMRAM
//    {
//        GETBUFFER : TYPE = DSECT
//        GETWRITEIDX : TYPE = DSECT
//        PUTREADIDX : TYPE = DSECT
//    }

}


__STACK_TOP = __stack + 256;