static void ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(uint32_t BaseAddress, uint16_t PeriodCountReload, LLCBRIDGE_Position_t Position) { uint32_t pwmPeriod_ticks; /* * compute PERIOD reload value to be loaded in HR registers */ pwmPeriod_ticks = (uint32_t)((float32_t)PeriodCountReload * 65536.0f);/* polyspace MISRA2012:10.8 [Justified:Low] "cast needed by application" */ /* * Direct access to HR PERIOD register * should be faster than using drivers */ HRPWM_setTimeBasePeriod(BaseAddress, pwmPeriod_ticks); HRPWM_setTimeBaseCounter(BaseAddress, 0); HRPWM_setPhaseShift(BaseAddress, 0); HRPWM_setTimeBaseCounterMode(BaseAddress, EPWM_COUNTER_MODE_UP_DOWN); HRPWM_setEmulationMode(BaseAddress, EPWM_EMULATION_FREE_RUN); /**< Set the dividers in order to match the value of EPWMCLK_LLC **/ HRPWM_setClockPrescaler(BaseAddress, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2); /**< Loads TBPRD on PERIOD **/ HRPWM_setPeriodLoadMode(BaseAddress, EPWM_PERIOD_SHADOW_LOAD); /* * * Action Qualifier Configuration in case of LLC_SYNCRECT_BY_PWM_TIMED * If Position == H1L2 * - TBCTR = CMPA @UP -> PWMx HIGH * - TBCTR = TBPRD -> PWMx LOW * * If Position == H2L1 * - TBCTR = CMPB @DOWN -> PWMx HIGH * - TBCTR = ZERO -> PWMx LOW */ HWREGH(BaseAddress + EPWM_O_AQCTLA) = 0x0000; /* * Generates PWM_A either from CMPA or CMPB (depends on Position) */ /**< Loads CMPA / CMPB on ZERO **/ HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO); if (Position == FB_H1L2_BRIDGE) { /**< Writes the init value into CMPA --> writes PRD in order to keep the output A LOW **/ HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint)); HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint)); HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); } else if (Position == FB_H2L1_BRIDGE) { /**< Writes the init value into CMPB --> writes ZERO in order to keep the output B LOW **/ HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint)); HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint)); HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); } else { /** does nothing **/ } /* * This setup is necessary in case of activation of HR (High Resolution) registers * --> see 18.7.2 Dead-band Submodule Additional Operating Modes * Otherwise the DB clock can be set as EPWM_DB_COUNTER_CLOCK_FULL_CYCLE */ /**< Deadband bypassed on RED **/ HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_RED, LLC_DB_RED_DELAY_MODE_DISABLE); /**< Deadband bypassed on FED --> this is not actually necessary since OUTB is generated by ePWM_A (RED)**/ HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_FED, LLC_DB_RED_DELAY_MODE_DISABLE); /**< OUTA from ePWM_A **/ HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_A, false); /**< OUTB from ePWM_A **/ HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_B, true); /* * High Resolution registers activation */ /* * this configuration is recommended if the HighResolution feature shall be used * see par. 18.15.1.5.4.1 High-Resolution Period Configuration */ /**< MEP control of rising edge (CMPAHR) **/ HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_EDGE); /**< MEP control of rising edge (CMPBHR) **/ HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_EDGE); /** NOTE FROM TRM * If the HRPWM module is configured in UP-DOWN counter mode, the shadow mode for the HRPWM * registers must be set to load on both ZERO AND PERIOD. New values from the user are loaded to * the shadow registers only at CTR=ZERO, but the shadow mode of for the registers must be set to * both ZERO AND PERIOD. **/ /**< HRCMPA loaded on ZERO **/ HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD); /**< HRCMPB loaded on ZERO **/ HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD); HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL); HRPWM_enableAutoConversion(BaseAddress); HRPWM_enablePeriodControl(BaseAddress); } /**< This function provides the clock to PWM used **/ void ABS_LLC_Enable_ePWM_Peripherals(void) { /** Safety Manual par 4.2.6 - comma 1 - CLK14-Peripheral clock gating **/ /* Peripherals for Primary LLC */ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM18); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); /**< Burst mode gating primary **/ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM17); /* Peripherals for Secondary LLC */ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM13); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); /**< Burst mode gating Secondary **/ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); /* This is necessary to use the High Resolution modulator --> see par. 18.15.1.2 HRPWM Source Clock */ /** Safety Manual par 4.2.6 - comma 1 - CLK14-Peripheral clock gating **/ SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL0); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL1); SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRCAL2); } /**-------------------------------------------------------------------------- * @fn void ABS_LLC_ConfigPWMs_LLCBridges(void) * @brief configures LLC ePWMs peripherals in order to generate synchronous rectification switching ON the synchronous PWM * in sync with driving PWM, and switching OFF based on CMPSSx output * @details Configures Phase Shift, SYNC Input source, TBPRD register link, CMPA/CMPB register link * @param[in] * @calls * @return */ static void ABS_LLC_ConfigPWMs_LLCBridges(void) { uint8_least Counter; Counter = 0; /* *< REMARK FOR TI SUPPORT * THIS LOOP CONFIGURES THE PWMs OF CLLC BRIDGE, DEPENDING ON THEIR POSITION IN THE BRIDGE * USES FUNCTION ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet THAT IS WRITTEN ABOVE */ while (Counter < NOF_LLC_PWMs) { ABS_LLC_PWMsTab_Descriptor_t *LLCTabDescriptorPtr; LLCTabDescriptorPtr = &TAB_ePWM_LLC_TableDescriptor[Counter]; /* * Configures the single pwm depending on the PWM position in LLC bridge * All PWMS are configured as UP DOWN counter */ ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(LLCTabDescriptorPtr->PWM_BaseAddress, (uint16_t)LLC_MIN_PRD_UD_MODE_COUNT, LLCTabDescriptorPtr->PWM_Position); Counter = Counter + 1u; } /* * Sets the shift phase and register links between ePWMs */ /**< PWM PRI LEG1 HS --> generates SYNCOUT **/ EPWM_disablePhaseShiftLoad(LLC_PRI_LEG1_HS_PWM_MODULE); EPWM_enableSyncOutPulseSource(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO); /* * PWM PRI LEG1 LS * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter * TBPRD is linked to PRI LEG1 HS */ EPWM_enablePhaseShiftLoad(LLC_PRI_LEG1_LS_PWM_MODULE); /** Sets the Sync In from Sync Out of the master (PWM8) **/ EPWM_setSyncInPulseSource(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); /** Count up after sync **/ EPWM_setCountModeAfterSync(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC); /** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_PRI_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); /* * PWM PRI LEG2 HS * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter * TBPRD is linked to PRI LEG1 HS * CMPB register is linked to PRI LEG1 LS */ EPWM_enablePhaseShiftLoad(LLC_PRI_LEG2_HS_PWM_MODULE); /** Sets the Sync In from Sync Out of the master (PWM8) **/ EPWM_setSyncInPulseSource(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); /** Count up after sync **/ EPWM_setCountModeAfterSync(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC); /** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); /** CMPB linked to CMPB of PRI 1 LS (ePWM18) **/ EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_B); /** CMPA linked to CMPA of PRI 1 LS (ePWM18) **/ EPWM_setupEPWMLinks(LLC_PRI_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A); /* * PWM PRI LEG2 LS * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter * TBPRD is linked to PRI LEG1 HS * CMPA register is linked to PRI LEG1 HS */ EPWM_enablePhaseShiftLoad(LLC_PRI_LEG2_LS_PWM_MODULE); /** Sets the Sync In from Sync Out of the master (PWM8) **/ EPWM_setSyncInPulseSource(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); /** Count up after sync **/ EPWM_setCountModeAfterSync(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC); /** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); /** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A); /** CMPB linked to CMPB of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_B); /**< Enables the ONE SHOT SYNC output --> used by PRI GATING BURST PWM to sync when entering BURST MODE **/ /**< This needs also the standard sync out enabled, because the synch-ed output takes as source the std sync out **/ /**< PAY ATTENTION: this is only a enable: SYNC must be commanded by sw **/ EPWM_enableSyncOutPulseSource(LLC_PRI_LEG2_LS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO); EPWM_enableOneShotSync(LLC_PRI_LEG2_LS_PWM_MODULE); /* * PWM SEC LEG1 HS * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter * TBPRD is linked to PRI LEG1 HS * CMPA register is linked to PRI LEG1 HS */ EPWM_enablePhaseShiftLoad(LLC_SEC_LEG1_HS_PWM_MODULE); /** Sets the Sync In from Sync Out of the master (PWM8) **/ EPWM_setSyncInPulseSource(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); /** Count up after sync **/ EPWM_setCountModeAfterSync(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC); /** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); /** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG1_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A); /* * PWM SEC LEG1 LS * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter * TBPRD is linked to PRI LEG1 HS * CMPB register is linked to PRI LEG1 LS */ EPWM_enablePhaseShiftLoad(LLC_SEC_LEG1_LS_PWM_MODULE); /** Sets the Sync In from Sync Out of the master (PWM8) **/ EPWM_setSyncInPulseSource(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); /** Count up after sync **/ EPWM_setCountModeAfterSync(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC); /** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); /** CMPA linked to CMPA of PRI 1 LS (ePWM18) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG1_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A); /* * PWM SEC LEG2 HS * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter * TBPRD is linked to PRI LEG1 HS * CMPB register is linked to PRI LEG1 LS */ EPWM_enablePhaseShiftLoad(LLC_SEC_LEG2_HS_PWM_MODULE); /** Sets the Sync In from Sync Out of the master (PWM8) **/ EPWM_setSyncInPulseSource(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); /** Count up after sync **/ EPWM_setCountModeAfterSync(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC); /** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); /** CMPA linked to CMPA of SEC 1 LS (ePWM7) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_18, EPWM_LINK_COMP_A); /** CMPB linked to CMPB of PRI 1 LS (ePWM18) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG2_HS_PWM_MODULE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_COMP_B); /* * PWM SEC LEG2 LS * Takes the SYNC IN from PRI LEG1 HS (ePWM1) to synchronize the TB counter * TBPRD is linked to PRI LEG1 HS * CMPA register is linked to PRI LEG1 HS */ EPWM_enablePhaseShiftLoad(LLC_SEC_LEG2_LS_PWM_MODULE); /** Sets the Sync In from Sync Out of the master (PWM8) **/ EPWM_setSyncInPulseSource(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); /** Count up after sync **/ EPWM_setCountModeAfterSync(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_COUNT_MODE_UP_AFTER_SYNC); /** TBPRD linked to TBPRD of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_TBPRD); /** CMPA linked to CMPA of PRI 1 HS (ePWM1) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_1, EPWM_LINK_COMP_A); /** CMP3 linked to CMP3 of SEC 1 HS (ePWM13) **/ EPWM_setupEPWMLinks(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_LINK_WITH_EPWM_13, EPWM_LINK_COMP_B); /**< Enables the ONE SHOT SYNC output --> used by SEC GATING BURST PWM to sync when entering BURST MODE **/ /**< This needs also the standard sync out enabled, because the synch-ed output takes as source the std sync out **/ /**< PAY ATTENTION: this is only a enable: SYNC must be commanded by sw **/ EPWM_enableSyncOutPulseSource(LLC_SEC_LEG2_LS_PWM_MODULE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO); EPWM_enableOneShotSync(LLC_SEC_LEG2_LS_PWM_MODULE); /* * Sets the initial compare value of CMPC --> used to trigger AD conversion of HVDC I / HVDC V * CMPC is set in the middle of duty cycle of PWMxA HIGH * This feature is used only with Primary LLC pwm to generate a SOC for IBAT and VBAT */ EPWM_setCounterCompareValue(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_COUNTER_COMPARE_C, (LLC_MIN_PRD_UD_MODE_COUNT >> 1u)); /* * Sets the LoadMode of CMPC --> used to trigger AD conversion */ EPWM_setCounterCompareShadowLoadMode(LLC_PRI_LEG1_HS_PWM_MODULE, EPWM_COUNTER_COMPARE_C, EPWM_COMP_LOAD_ON_CNTR_ZERO); }