static void ABS_LLC_ConfigSingleLLC_DrivingAndSyncMosfet(uint32_t BaseAddress, uint16_t PeriodCountReload, LLCBRIDGE_Position_t Position)
{

    uint32_t pwmPeriod_ticks;


	/*
	 * compute PERIOD reload value to be loaded in HR registers
	 */
	pwmPeriod_ticks = (uint32_t)((float32_t)PeriodCountReload * 65536.0f);/* polyspace MISRA2012:10.8 [Justified:Low] "cast needed by application" */



    /*
	 * Direct access to HR PERIOD register
	 * should be faster than using drivers
	 */
    HRPWM_setTimeBasePeriod(BaseAddress, pwmPeriod_ticks);


    HRPWM_setTimeBaseCounter(BaseAddress, 0);
    HRPWM_setPhaseShift(BaseAddress, 0);
    HRPWM_setTimeBaseCounterMode(BaseAddress, EPWM_COUNTER_MODE_UP_DOWN);
    HRPWM_setEmulationMode(BaseAddress, EPWM_EMULATION_FREE_RUN);
	
	/**< Set the dividers in order to match the value of EPWMCLK_LLC **/
	HRPWM_setClockPrescaler(BaseAddress, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_2);



	/**< Loads TBPRD on PERIOD **/
    HRPWM_setPeriodLoadMode(BaseAddress, EPWM_PERIOD_SHADOW_LOAD);





	/*
	 *
	 * Action Qualifier Configuration in case of LLC_SYNCRECT_BY_PWM_TIMED
	 * If Position == H1L2
	 * - TBCTR = CMPA @UP -> PWMx HIGH
	 * - TBCTR = TBPRD -> PWMx LOW
	 *
	 * If Position == H2L1
	 * - TBCTR = CMPB @DOWN -> PWMx HIGH
	 * - TBCTR = ZERO -> PWMx LOW
	 */

    HWREGH(BaseAddress + EPWM_O_AQCTLA) = 0x0000;

	/*
	 * Generates PWM_A either from CMPA or CMPB (depends on Position)
	 */

	/**< Loads CMPA / CMPB on ZERO **/
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO);
	HRPWM_setCounterCompareShadowLoadMode(BaseAddress, EPWM_COUNTER_COMPARE_B, EPWM_COMP_LOAD_ON_CNTR_ZERO);

	if (Position == FB_H1L2_BRIDGE) {

 		/**< Writes the init value into CMPA --> writes PRD in order to keep the output A LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
	}

	else if (Position == FB_H2L1_BRIDGE) {

 		/**< Writes the init value into CMPB --> writes ZERO in order to keep the output B LOW **/
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_A, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));
		HRPWM_setCounterCompareValue(BaseAddress, HRPWM_COUNTER_COMPARE_B, LLC_PWM_HR_TRANSFORM(LLC_OFF_Duty_StartPoint));

		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
		HRPWM_setActionQualifierAction(BaseAddress, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
	}

	else {
		/** does nothing **/
	}






	/*
	 * This setup is necessary in case of activation of HR (High Resolution) registers
	 * --> see 18.7.2 Dead-band Submodule Additional Operating Modes
	 * Otherwise the DB clock can be set as EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
	 */

    /**< Deadband bypassed on RED **/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_RED, LLC_DB_RED_DELAY_MODE_DISABLE);
    /**< Deadband bypassed on FED --> this is not actually necessary since OUTB is generated by ePWM_A (RED)**/
	HRPWM_setDeadBandDelayMode(BaseAddress, EPWM_DB_FED, LLC_DB_RED_DELAY_MODE_DISABLE);

	/**< OUTA from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_A, false);

	/**< OUTB from ePWM_A **/
	HRPWM_setDeadBandOutputSwapMode(BaseAddress, EPWM_DB_OUTPUT_B, true);










	/*
	 * High Resolution registers activation
	 */
	/*
	 * this configuration is recommended if the HighResolution feature shall be used
	 * see par. 18.15.1.5.4.1 High-Resolution Period Configuration
	 */
	/**< MEP control of rising edge (CMPAHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_CTRL_RISING_EDGE);
	/**< MEP control of rising edge (CMPBHR) **/
    HRPWM_setMEPEdgeSelect(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_CTRL_RISING_EDGE);


	/** NOTE FROM TRM
	* If the HRPWM module is configured in UP-DOWN counter mode, the shadow mode for the HRPWM
	* registers must be set to load on both ZERO AND PERIOD. New values from the user are loaded to
	* the shadow registers only at CTR=ZERO, but the shadow mode of for the registers must be set to
	* both ZERO AND PERIOD.
	**/
	/**< HRCMPA loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);
	/**< HRCMPB loaded on ZERO **/
	HRPWM_setCounterCompareShadowLoadEvent(BaseAddress, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);

    HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_A, HRPWM_MEP_DUTY_PERIOD_CTRL);
	HRPWM_setMEPControlMode(BaseAddress, HRPWM_CHANNEL_B, HRPWM_MEP_DUTY_PERIOD_CTRL);

    HRPWM_enableAutoConversion(BaseAddress);

    HRPWM_enablePeriodControl(BaseAddress);

}