#if 1
#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

#pragma CODE_SECTION(InitFlash, "ramfuncs");

#define CPU_FREQ 	 150E6
#define LSPCLK_FREQ  CPU_FREQ/4
#define SCI_FREQ 	 100E3
#define SCI_PRD 	 (LSPCLK_FREQ/(SCI_FREQ*8))-1

// Prototype statements for functions found within this file.
//__interrupt void scicTxFifoIsr(void);
__interrupt void scicRxFifoIsr(void);
void scic_fifo_init(void);
void InitScicGpio();

Uint16 rdataB[8];    // Received data for SCI-A

extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;
extern Uint16 RamfuncsLoadSize;

void Delay()
{
	unsigned int i,j;
	for(i = 0;i < 500;i++)
		for(j = 0;j < 500;j++);
}

Uint16 Recv_dat = 0x00;
void main(void)
{
   Uint16 i;
   unsigned char SendChar = 0x00;

   InitSysCtrl();
   InitScicGpio();
   DINT;

   InitPieCtrl();
   IER = 0x0000;
   IFR = 0x0000;
   InitPieVectTable();

   MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
   InitFlash();

   EALLOW;
   PieVectTable.SCIRXINTC = &scicRxFifoIsr;
//   PieVectTable.SCITXINTB = &scibTxFifoIsr;
   EDIS;

   scic_fifo_init();  // Init SCI-B

   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER8.bit.INTx5 = 1;     // PIE Group 9, INT3
//   PieCtrlRegs.PIEIER8.bit.INTx6=1;     // PIE Group 9, INT4
   IER |= 0x080;
   EINT;

   while(1)
   {
	   for(i = 0;i < 8;i++)
	   {
		   ScicRegs.SCITXBUF=0x55;//SendChar;
		   Delay();Delay();Delay();Delay();
		   Delay();Delay();Delay();Delay();
//		   ScicRegs.SCICTL1.bit.RXENA = 1;
//		   Delay();Delay();Delay();Delay();
//		   while(ScicRegs.SCIFFTX.bit.TXFFST != 0);
		   SendChar++;
		   SendChar &= 0xFF;
	   }
	   Delay();Delay();Delay();Delay();
   }
}
/*
__interrupt void scibTxFifoIsr(void)
{
    Uint16 i;
    for(i=0; i< 8; i++)
    {
 	   ScibRegs.SCITXBUF=sdataB[i];     // Send data
	}

    for(i=0; i< 8; i++)                 //Increment send data for next cycle
    {
 	   sdataB[i] = (sdataB[i]-1) & 0x00FF;
	}

	ScibRegs.SCIFFTX.bit.TXFFINTCLR=1;  // Clear Interrupt flag
	PieCtrlRegs.PIEACK.all|=0x100;      // Issue PIE ACK
}
*/
__interrupt void scicRxFifoIsr(void)
{
    Uint16 i;
unsigned char dat = 0x0, dat1 = 0x0;

//    dat = ScicRegs.SCIRXST.bit.RXRDY;
//Recv_dat = ScicRegs.SCIRXEMU;	 // Read data

    Recv_dat = ScicRegs.SCIRXBUF.all;	 // Read data
//    dat = ScicRegs.SCIRXST.all;
//    dat1 = ScicRegs.SCIRXST.bit.RXRDY;
    for(i=0;i<8;i++)
	{
//	   rdataB[i] = ScicRegs.SCIRXBUF.all;	 // Read data
	}

	ScicRegs.SCIFFRX.bit.RXFFOVRCLR=1;  // Clear Overflow flag
	ScicRegs.SCIFFRX.bit.RXFFINTCLR=1; 	// Clear Interrupt flag
	PieCtrlRegs.PIEACK.all|=0x080;  	// Issue PIE ack
}

void scic_fifo_init()
{
   ScicRegs.SCICCR.all =0x0007;    // 1 stop bit,  No loopback
                                   // No parity,8 char bits,
                                   // async mode, idle-line protocol
   ScicRegs.SCICTL1.all =0x0003;   // enable TX, RX, internal SCICLK,
                                   // Disable RX ERR, SLEEP, TXWAKE
//   ScicRegs.SCICTL2.bit.TXINTENA =1;
   ScicRegs.SCICTL2.bit.RXBKINTENA =1;
   ScicRegs.SCIHBAUD    = 0x01;
   ScicRegs.SCILBAUD    = 0xE7;//SCI_PRD;
   ScicRegs.SCICCR.bit.LOOPBKENA =0; // Enable loop back
   ScicRegs.SCIFFTX.all=0xC021;
   ScicRegs.SCIFFRX.all=0x0021;
   ScicRegs.SCIFFCT.all=0x00;

   ScicRegs.SCICTL1.all =0x0023;     // Relinquish SCI from Reset
   ScicRegs.SCIFFTX.bit.TXFIFOXRESET=1;
   ScicRegs.SCIFFRX.bit.RXFIFORESET=1;
}

void InitScicGpio()
{
   EALLOW;

   GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0;    // Enable pull-up for GPIO62 (SCIRXDC)
   GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0;	   // Enable pull-up for GPIO63 (SCITXDC)

	GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3;  // Asynch input GPIO62 (SCIRXDC)

	GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1;   // Configure GPIO62 for SCIRXDC operation
	GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1;   // Configure GPIO63 for SCITXDC operation

//	GpioCtrlRegs.GPBDIR.bit.GPIO62 = 0;   // Configure GPIO63 for SCITXDC operation
//	GpioCtrlRegs.GPBDIR.bit.GPIO63 = 1;   // Configure GPIO63 for SCITXDC operation
    EDIS;
}
#endif