MEMORY
{
   BEGIN            : origin = 0x080000, length = 0x000002  // Update the codestart location as needed

   BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
   RAMM0            : origin = 0x0001B1, length = 0x00024F
   RAMM1            : origin = 0x000400, length = 0x000400

   RAMD0            : origin = 0x00C000, length = 0x002000
   RAMD1            : origin = 0x00E000, length = 0x002000
   RAMD2            : origin = 0x01A000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
   RAMD3            : origin = 0x01C000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
   RAMD4            : origin = 0x01E000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
   RAMD5            : origin = 0x020000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection

   RAMLS01234         : origin = 0x008000, length = 0x002800
   //RAMLS1           : origin = 0x008800, length = 0x000800
   //RAMLS2           : origin = 0x009000, length = 0x000800
    //RAMLS3          : origin = 0x009800, length = 0x000800
   //RAMLS4           : origin = 0x00A000, length = 0x000800
   RAMLS5           : origin = 0x00A800, length = 0x000800
   RAMLS6           : origin = 0x00B000, length = 0x000800
   RAMLS7           : origin = 0x00B800, length = 0x000800
   RAMLS8           : origin = 0x022000, length = 0x002000  // When configured as CLA program use the address 0x4000
   RAMLS9           : origin = 0x024000, length = 0x002000  // When configured as CLA program use the address 0x6000

   // RAMLS8_CLA    : origin = 0x004000, length = 0x002000  // Use only if configured as CLA program memory
   // RAMLS9_CLA    : origin = 0x006000, length = 0x002000  // Use only if configured as CLA program memory

   RAMGS0           : origin = 0x010000, length = 0x002000
   RAMGS1           : origin = 0x012000, length = 0x002000
   RAMGS2           : origin = 0x014000, length = 0x002000
   RAMGS3_4           : origin = 0x016000, length = 0x004000
   //RAMGS4           : origin = 0x018000, length = 0x002000

   /* Flash Banks (128 sectors each) */
   //FLASH_BANK0     : origin = 0x080002, length = 0x007FFE  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   //BOOT_FLASH       : origin = 0x080002, length = 0x007FFE

   BOOT_FLASH        : origin = 0x080002, length = 0x007FFE	/* on-chip Flash */
   APP_FLASH         : origin = 0x088000, length = 0x018000	/* on-chip Flash */

   FLASH_BANK1     : origin = 0x0A0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   FLASH_BANK2     : origin = 0x0C0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   // FLASH_BANK3     : origin = 0x0E0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
   // FLASH_BANK4     : origin = 0x100000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection



   CPU1TOCPU2RAM    : origin = 0x03A000, length = 0x000400
   CPU2TOCPU1RAM    : origin = 0x03B000, length = 0x000400

   CLATOCPURAM      : origin = 0x001480,   length = 0x000080
   CPUTOCLARAM      : origin = 0x001500,   length = 0x000080
   CLATODMARAM      : origin = 0x001680,   length = 0x000080
   DMATOCLARAM      : origin = 0x001700,   length = 0x000080

   CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
   CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
   RESET            : origin = 0x3FFFC0, length = 0x000002
}


SECTIONS
{
   codestart        : > BEGIN
   .text            : >> APP_FLASH, ALIGN(8)
   .cinit           : > APP_FLASH, ALIGN(8)
   .switch          : > APP_FLASH, ALIGN(8)
   .reset           : > RESET, TYPE = DSECT /* not used, */

   .stack           : > RAMM1
#if defined(__TI_EABI__)
   .bss             : > RAMLS9
   .bss:output      : > RAMLS9
   .init_array      : > APP_FLASH, ALIGN(8)
   .const           : > APP_FLASH, ALIGN(8)
   .data            : > RAMLS7 | RAMLS8
   .sysmem          : > RAMLS5
#else
   .pinit           : > APP_FLASH, ALIGN(8)
   .ebss            : >> RAMLS5 | RAMLS6
                       START(_start_ebss)
                       END(_end_ebss)

   .econst          : > APP_FLASH, ALIGN(8)
   .esysmem         : > RAMLS5
#endif

   ramgs0 : > RAMGS0, type=NOINIT
   ramgs1 : > RAMGS1, type=NOINIT
   ramgs2 : > RAMGS2, type=NOINIT



 /*boot memory allocation */
   boot_cinit
   {

      -l FAPI_F28P65x_EABI_v3.00.02.lib (.cinit)
         boot_main.obj(.cinit)
         boot_hwinit.obj(.cinit)
         boot_flash.obj(.cinit)
         boot_flash.obj(.econst)

   } > BOOT_FLASH

    boot_start
    {
          entry.obj (.text)//entry //f28p65x_codestartbranch
          boot_main.obj(.text)
          boot_hwinit.obj(.text)
          boot_flash.obj(.text)

    } > BOOT_FLASH

   boot_flash_lib :
   {
 	  -l FAPI_F28P65x_EABI_v3.00.02.lib (.econst)
 	  -l FAPI_F28P65x_EABI_v3.00.02.lib (.text)

   } LOAD = BOOT_FLASH,
     RUN = RAMLS01234,
     LOAD_START(_boot_flash_code_load_start),
     LOAD_SIZE(_boot_flash_code_size),
     RUN_START(_boot_flash_code_run_start)


   .data_boot
   {
           entry.obj (.data) //entry //f28p65x_codestartbranch
           boot_main.obj (.data)
           boot_hwinit.obj (.data)
           boot_flash.obj(.data)
           -l FAPI_F28P65x_EABI_v3.00.02.lib (.data)

   } > RAMM1

   .ebss_boot
   {
           entry.obj (.ebss) //f28p65x_codestartbranch
           boot_main.obj (.ebss)
           boot_hwinit.obj (.ebss)
           boot_flash.obj(.ebss)
           -l FAPI_F28P65x_EABI_v3.00.02.lib (.ebss)

   } > RAMM1

 /* Allocate program areas: */
  // bootstrap
  // {
  //       entry.obj (.text)
  //  // - l FAPI_F28P65x_EABI_v3.00.02.lib (.cinit)
  //
  // } > APP_FLASH //0x088000


   fapi             : > BOOT_FLASH
   {
       --library = FAPI_F28P65x_EABI_v3.00.02.lib

   }, ALIGN(8)



  // #if defined(__TI_EABI__)
       .TI.ramfunc : {} LOAD = APP_FLASH,
                        RUN = RAMGS3_4,//RAMLS01234,
                        LOAD_START(RamfuncsLoadStart),
                        LOAD_SIZE(RamfuncsLoadSize),
                        LOAD_END(RamfuncsLoadEnd),
                        RUN_START(RamfuncsRunStart),
                        RUN_SIZE(RamfuncsRunSize),
                        RUN_END(RamfuncsRunEnd),
                        ALIGN(8)
   //#else
   //    .TI.ramfunc : {} LOAD = APP_FLASH,
   //                     RUN = RAMGS3_4,
   //                     LOAD_START(_RamfuncsLoadStart),
   //                     LOAD_SIZE(_RamfuncsLoadSize),
   //                     LOAD_END(_RamfuncsLoadEnd),
   //                     RUN_START(_RamfuncsRunStart),
   //                     RUN_SIZE(_RamfuncsRunSize),
   //                     RUN_END(_RamfuncsRunEnd),
   //                     ALIGN(8)
   //#endif



   MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM,                type=NOINIT
   MSGRAM_CPU1_TO_CPU2_COPY_TO_M1_RAM > CPU1TOCPU2RAM, type=NOINIT
   MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM,                type=NOINIT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/