EALLOW;


    //
    // Initialise and wait for CLA1ToCPUMsgRAM
    //
    MemCfgRegs.MSGxINIT.all = 0x00000004;
    while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CLA1TOCPU != 1);

    //
    // Initialise and wait for CPUToCLA1MsgRAM
    //
    MemCfgRegs.MSGxINIT.all = 0x00000002;
    while(MemCfgRegs.MSGxINITDONE.bit.INITDONE_CPUTOCLA1 != 1);

    //
    // Select LS2 to be the programming space for the CLA
    // First configure the CLA to be the master for LS2 and then
    // set the space to be a program block
    //
    MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 0x1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0x1;

    //
    // Next configure LS0RAM and LS1RAM as data spaces for the CLA
    // First configure the CLA to be the master for LS0(1) and then
    // set the spaces to be code blocks
    //
    MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 0x1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0x0;
    MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 0x1;
    MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0x0;

    EDIS;