//
#include "F28x_Project.h"

//
// Defines
//
#define TXFIFO_LVL          8 // FIFO Interrupt Level
#define TXBURST             (16-TXFIFO_LVL)-1 // burst size should be less than 8
#define TXTRANSFER          (uint32_t)((20/(16-TXFIFO_LVL)) - 1) // [(MEM_BUFFER_SIZE/FIFO_LVL)-1]

#define RXFIFO_LVL          8 // FIFO Interrupt Level
#define RXBURST             RXFIFO_LVL-1 // burst size should be less than 8
#define RXTRANSFER          (uint32_t)((20/RXFIFO_LVL) - 1) // [(MEM_BUFFER_SIZE/FIFO_LVL)-1]

//
// Globals
//
#pragma DATA_SECTION(sdataA, "ramgs0"); // map the TX data to memory
//#pragma DATA_SECTION(rdataA, "ramgs1"); // map the RX data to memory
//#pragma DATA_SECTION(sdataB, "ramgs0"); // map the TX data to memory
#pragma DATA_SECTION(rdataB, "ramgs0"); // map the RX data to memory
Uint16 sdataA[20]; // Send data buffer
Uint16 rdataB[20]; // Receive data buffer


volatile Uint16 *DMADest;
volatile Uint16 *DMASource;

void dma_init(void);
void spi_fifo_init(void);

//
// Main
//
void main(void)
{
    Uint16 i;

    InitSysCtrl();
    //InitSpiaGpio();
    //InitSpibGpio();

    DINT;
    IER = 0x0000;
    IFR = 0x0000;
    InitPieCtrl();
    InitPieVectTable();
    //
    // Step 4. Initialize the Device Peripherals:
    //
    dma_init(); // Set up DMA for SPI configuration

    EALLOW;
    CpuSysRegs.SECMSEL.bit.PF2SEL = 1; // Ensure DMA is connected to Peripheral Frame 2 bridge (EALLOW protected)
    //CpuSysRegs.SECMSEL.bit.PF1SEL = 1; // Ensure DMA is connected to Peripheral Frame 2 bridge (EALLOW protected)

    EDIS;
    spi_fifo_init(); // Initialize the SPI only
    //
    // Initialize the data buffers
    //
    for(i=0; i<20; i++)
    {
        sdataA[i] = i;
        rdataB[i] = 0;
    }

    while(1)
    {
        StartDMACH6();
        StartDMACH5();
    }
}

//
// spi_fifo_init - Initialize SPIA FIFO
//
void spi_fifo_init()
{
    // SPIA FIFO regesters conf
    SpibRegs.SPIFFTX.bit.TXFFIL = TXFIFO_LVL;
    SpibRegs.SPIFFRX.bit.RXFFIL = RXFIFO_LVL; // Set RX FIFO level
    SpiaRegs.SPIFFTX.bit.TXFFIL = TXFIFO_LVL; // Set TX FIFO level
    SpiaRegs.SPIFFRX.bit.RXFFIL = RXFIFO_LVL;
    SpiaRegs.SPIFFTX.bit.SPIFFENA = 1;
    SpiaRegs.SPIFFTX.bit.TXFFINTCLR = 1;
    SpiaRegs.SPIFFRX.bit.RXFFINTCLR = 1;
    SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1;
    SpiaRegs.SPIFFTX.bit.TXFIFO = 1;
    SpiaRegs.SPIFFRX.bit.RXFIFORESET = 1;
    SpiaRegs.SPIFFTX.bit.SPIRST = 1;
    // SPIB FIFO regesters conf
    SpibRegs.SPIFFTX.bit.SPIFFENA = 1;
    SpibRegs.SPIFFTX.bit.TXFFINTCLR = 1;
    SpibRegs.SPIFFRX.bit.RXFFINTCLR = 1;
    SpibRegs.SPIFFRX.bit.RXFFOVFCLR = 1;
    SpibRegs.SPIFFTX.bit.TXFIFO = 1;
    SpibRegs.SPIFFRX.bit.RXFIFORESET = 1;
    SpibRegs.SPIFFTX.bit.SPIRST = 1;

    //
    // Initialize core SPIA registers
    //
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpiaRegs.SPICCR.bit.SPICHAR = (16-1);
 //   SpiaRegs.SPICCR.bit.SPILBK = 1;

    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1;
    SpiaRegs.SPICTL.bit.TALK = 1;
    SpiaRegs.SPICTL.bit.CLK_PHASE = 0;
    SpiaRegs.SPICTL.bit.SPIINTENA = 0;
    // Set the baud rate
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 0x0f;//SPI_BRR;

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    SpiaRegs.SPIPRI.bit.FREE = 1;

    // Release the SPI from reset
    SpiaRegs.SPICCR.bit.SPISWRESET = 1;

    // Initialize core SPIB registers
    SpibRegs.SPICCR.bit.SPISWRESET = 0;
    SpibRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpibRegs.SPICCR.bit.SPICHAR = (16-1);
  //  SpibRegs.SPICCR.bit.SPILBK = 1;

    SpibRegs.SPICTL.bit.MASTER_SLAVE = 0;
    SpibRegs.SPICTL.bit.TALK = 1;
    SpibRegs.SPICTL.bit.CLK_PHASE = 0;
    SpibRegs.SPICTL.bit.SPIINTENA = 0;

    // Set the baud rate
    SpibRegs.SPIBRR.bit.SPI_BIT_RATE = 0x0f;//SPI_BRR;

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    SpibRegs.SPIPRI.bit.FREE = 1;

    // Release the SPI from reset
    SpibRegs.SPICCR.bit.SPISWRESET = 1;
}

//
// dma_init - DMA setup for both TX and RX channels.
//
void dma_init()
{
    //
    // Initialize DMA
    //
    DMAInitialize();
    //DMASource = (volatile Uint16 *)sdata;
    //DMADest = (volatile Uint16 *)rdata;

    //
    // configure DMACH5 for SPI A TX
    //
    DMACH5AddrConfig(&SpiaRegs.SPITXBUF,sdataA);
    DMACH5BurstConfig(TXBURST,1,0); // Burst size, src step, dest step
    DMACH5TransferConfig(TXTRANSFER,1,0); // transfer size, src step, dest step
    DMACH5ModeConfig(DMA_SPIATX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,
    SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
    CHINT_END,CHINT_DISABLE);

    //
    // configure DMA CH6 for SPI B RX
    //
    DMACH6AddrConfig(rdataB,&SpibRegs.SPIRXBUF);
    DMACH6BurstConfig(RXBURST,0,1);
    DMACH6TransferConfig(RXTRANSFER,0,1);
    DMACH6ModeConfig(DMA_SPIBRX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_ENABLE,
    SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
    CHINT_END,CHINT_DISABLE);
}
//
// End of file
//