1/*



2 * File: pwm.c



3 *



4 * Code generated for Simulink model 'pwm'.



5 *



6 * Model version                  : 1.48



7 * Simulink Coder version         : 8.12 (R2017a) 16-Feb-2017



8 * C/C++ source code generated on : Thu Jan 11 09:58:52 2018



9 *



10 * Target selection: ert.tlc



11 * Embedded hardware selection: Texas Instruments->C2000



12 * Code generation objectives: Unspecified



13 * Validation result: Not run



14 */



15



16#include "pwm.h"



17#include "pwm_private.h"



18



19/* Real-time model */



20RT_MODEL_pwm_T pwm_M_;



21RT_MODEL_pwm_T *const pwm_M = &pwm_M_;



22



23/* Model step function */



24void pwm_step(void)



25{



26  /* (no output/update code required) */



27}



28



29/* Model initialize function */



30void pwm_initialize(void)



31{



32  /* Registration code */



33



34  /* initialize error status */



35  rtmSetErrorStatus(pwm_M, (NULL));



36



37  /* Start for S-Function (c280xpwm): '<Root>/S1,S2' */



38



39  /*** Initialize ePWM1 modules ***/



40  {



41    /*-- Setup Time-Base (TB) Submodule --*/



42    EPwm1Regs.TBPRD = 15000;



43



44    /* // Time-Base Control Register



45       EPwm1Regs.TBCTL.bit.CTRMODE    = 2;          // Counter Mode



46       EPwm1Regs.TBCTL.bit.SYNCOSEL   = 3;          // Sync output select



47       EPwm1Regs.TBCTL.bit.PRDLD      = 0;          // Shadow select



48       EPwm1Regs.TBCTL.bit.PHSEN      = 0;          // Phase load enable



49       EPwm1Regs.TBCTL.bit.PHSDIR     = 0;          // Phase Direction



50       EPwm1Regs.TBCTL.bit.HSPCLKDIV  = 0;          // High speed time pre-scale



51       EPwm1Regs.TBCTL.bit.CLKDIV     = 0;          // Timebase clock pre-scale



52     */



53    EPwm1Regs.TBCTL.all = (EPwm1Regs.TBCTL.all & ~0x3FBF) | 0x32;



54



55    /* // Time-Base Phase Register



56       EPwm1Regs.TBPHS.half.TBPHS     = 0;          // Phase offset register



57     */



58    EPwm1Regs.TBPHS.all = (EPwm1Regs.TBPHS.all & ~0xFFFF0000) | 0x0;



59    EPwm1Regs.TBCTR = 0x0000;          /* Clear counter*/



60



61    /*-- Setup Counter_Compare (CC) Submodule --*/



62    /* // Counter-Compare Control Register



63       EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;  // Compare A block operating mode.



64       EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;  // Compare B block operating mode.



65       EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;          // Active compare A



66       EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;          // Active compare A



67     */



68    EPwm1Regs.CMPCTL.all = (EPwm1Regs.CMPCTL.all & ~0x5F) | 0x0;



69    EPwm1Regs.CMPA.half.CMPA = 7500;



70    EPwm1Regs.CMPB = 7500;



71



72    /*-- Setup Action-Qualifier (AQ) Submodule --*/



73    EPwm1Regs.AQCTLA.all = 96;



74    EPwm1Regs.AQCTLB.all = 0;



75



76    /* // Action-Qualifier Software Force Register



77       EPwm1Regs.AQSFRC.bit.RLDCSF    = 0;          // Reload from Shadow options



78     */



79    EPwm1Regs.AQSFRC.all = (EPwm1Regs.AQSFRC.all & ~0xC0) | 0x0;



80



81    /* // Action-Qualifier Continuous S/W Force Register Set



82       EPwm1Regs.AQCSFRC.bit.CSFA     = 0;          // Continuous Software Force on output A



83       EPwm1Regs.AQCSFRC.bit.CSFB     = 0;          // Continuous Software Force on output B



84     */



85    EPwm1Regs.AQCSFRC.all = (EPwm1Regs.AQCSFRC.all & ~0xF) | 0x0;



86



87    /*-- Setup Dead-Band Generator (DB) Submodule --*/



88    /* // Dead-Band Generator Control Register



89       EPwm1Regs.DBCTL.bit.OUT_MODE   = 3;          // Dead Band Output Mode Control



90       EPwm1Regs.DBCTL.bit.IN_MODE    = 0;          // Dead Band Input Select Mode Control



91       EPwm1Regs.DBCTL.bit.POLSEL     = 2;          // Polarity Select Control



92     */



93    EPwm1Regs.DBCTL.all = (EPwm1Regs.DBCTL.all & ~0x3F) | 0xB;



94    EPwm1Regs.DBRED = 300;



95    EPwm1Regs.DBFED = 300;



96



97    /*-- Setup Event-Trigger (ET) Submodule --*/



98    /* // Event-Trigger Selection and Event-Trigger Pre-Scale Register



99       EPwm1Regs.ETSEL.bit.SOCAEN     = 1;          // Start of conversion A Enable



100       EPwm1Regs.ETSEL.bit.SOCASEL    = 1;          // Start of conversion A Select



101       EPwm1Regs.ETPS.bit.SOCAPRD     = 1;          // EPWM1SOCA Period Select



102       EPwm1Regs.ETSEL.bit.SOCBEN     = 0;          // Start of conversion B Enable



103       EPwm1Regs.ETSEL.bit.SOCBSEL    = 1;          // Start of conversion B Select



104       EPwm1Regs.ETPS.bit.SOCBPRD     = 1;          // EPWM1SOCB Period Select



105       EPwm1Regs.ETSEL.bit.INTEN      = 0;          // EPWM1INTn Enable



106       EPwm1Regs.ETSEL.bit.INTSEL     = 1;          // EPWM1INTn Select



107       EPwm1Regs.ETPS.bit.INTPRD      = 1;          // EPWM1INTn Period Select



108     */



109    EPwm1Regs.ETSEL.all = (EPwm1Regs.ETSEL.all & ~0xFF0F) | 0x1901;



110    EPwm1Regs.ETPS.all = (EPwm1Regs.ETPS.all & ~0x3303) | 0x1101;



111



112    /*-- Setup PWM-Chopper (PC) Submodule --*/



113    /* // PWM-Chopper Control Register



114       EPwm1Regs.PCCTL.bit.CHPEN      = 0;          // PWM chopping enable



115       EPwm1Regs.PCCTL.bit.CHPFREQ    = 0;          // Chopping clock frequency



116       EPwm1Regs.PCCTL.bit.OSHTWTH    = 0;          // One-shot pulse width



117       EPwm1Regs.PCCTL.bit.CHPDUTY    = 0;          // Chopping clock Duty cycle



118     */



119    EPwm1Regs.PCCTL.all = (EPwm1Regs.PCCTL.all & ~0x7FF) | 0x0;



120



121    /*-- Set up Trip-Zone (TZ) Submodule --*/



122    EALLOW;



123    EPwm1Regs.TZSEL.all = 0;



124



125    /* // Trip-Zone Control Register



126       EPwm1Regs.TZCTL.bit.TZA        = 3;          // TZ1 to TZ6 Trip Action On EPWM1A



127       EPwm1Regs.TZCTL.bit.TZB        = 3;          // TZ1 to TZ6 Trip Action On EPWM1B



128     */



129    EPwm1Regs.TZCTL.all = (EPwm1Regs.TZCTL.all & ~0xF) | 0xF;



130



131    /* // Trip-Zone Enable Interrupt Register



132       EPwm1Regs.TZEINT.bit.OST       = 0;          // Trip Zones One Shot Int Enable



133       EPwm1Regs.TZEINT.bit.CBC       = 0;          // Trip Zones Cycle By Cycle Int Enable



134     */



135    EPwm1Regs.TZEINT.all = (EPwm1Regs.TZEINT.all & ~0x6) | 0x0;



136    EDIS;



137  }



138}



139



140/* Model terminate function */



141void pwm_terminate(void)



142{



143  /* (no terminate code required) */



144}



145



146/*



147 * File trailer for generated code.



148 *



149 * [EOF]



150 */



151