* .subckt DMC1030UFDB_lib:DMC1030UFDB:schematic N_D N_G N_S P_D P_G P_S _M=1 CCGD P_node13 P_node14 C=9.5e-10 M $.model $W $L CCGS P_node2 P_node3 C=7.966e-10 M $.model $W $L DD1 P_node13 P_node12 DLIM m DD2 P_S P_node15 DLIM m DDDG P_node14 P_node15 DCGD m DDSD P_D P_node3 DSUB m MM1 P_node1 P_node2 P_node3 P_node3 PMOS w=1e-06 l=1e-06 Ad As Pd Ps Nrd Nrs Geo m CPage1_CGD _node13 _node14 C=1.22e-09 M $.model $W $L CPage1_CGS _node2 _node3 C=8.902e-10 M $.model $W $L DPage1_D1 _node12 _node13 DLIM m DPage1_D2 _node15 0 DLIM m DPage1_DDG _node15 _node14 DCGD m DPage1_DSD _node3 N_D DSUB m MPage1_M1 _node1 _node2 _node3 _node3 NMOS w=1e-06 l=1e-06 Ad As Pd Ps Nrd Nrs Geo m RPage1_R1 _node13 0 1 M $.model $W $L RPage1_R2 _node12 _node15 1 M $.model $W $L RPage1_RD N_D _node1 0.01313 M $.model $W $L RPage1_RG N_G _node2 1.63 M $.model $W $L RPage1_RS N_S _node3 0.001 M $.model $W $L RR1 P_node13 P_S 1 M $.model $W $L RR2 P_node12 P_node15 1 M $.model $W $L RRD P_D P_node1 0.03274 M $.model $W $L RRG P_G P_node2 4.88 M $.model $W $L RRS P_S P_node3 0.001 M $.model $W $L .ends DMC1030UFDB_lib:DMC1030UFDB:schematic .subckt FET simulation_lib:LM5112:schematic IN IN_B IN_REF VCC OUT VEE _M=1 CC_C1 VEE OUT C=1.4e-09 M $.model $W $L xX_U12 N14862041 N14869697 N14859687 IN_REF FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic m=1 VTHRESH=6 DELAY=2.5e-08 xX_U13 N14861648 N14869610 N14859687 IN_REF FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic m=1 VTHRESH=6 DELAY=2.5e-08 xX_U16 N14859687 N14862041 IN IN_REF FET simulation_lib:INPUTHYST_BASIC_GEN:schematic m=1 VTHRESH=1.55 VHYST=0.4 xX_U17 N14859687 N14861778 IN_B IN_REF FET simulation_lib:INPUTHYST_BASIC_GEN:schematic m=1 VTHRESH=1.55 VHYST=0.4 xX_U18 N14875621 IN_REF N14860433 VEE FET simulation_lib:LS_BASIC_GEN:schematic m=1 xX_U21 N14861778 N14861648 N14859687 IN_REF FET simulation_lib:INVERTER_BASIC_GEN:schematic m=1 VTHRESH=6 xX_U22 N14869787 N14869697 N14869610 N14875621 N14859687 IN_REF FET simulation_lib:NAND3_BASIC_GEN:schematic m=1 VTHRESH=6 xX_U3 N14859687 N14869787 VCC IN_REF FET simulation_lib:UVLO_BASIC_GEN:schematic m=1 VTHRESH=3 VHYST=0.23 xX_U8 VCC OUT N14860433 VEE FET simulation_lib:VSW_BASIC_GEN:schematic m=1 RON=2 ROFF=1000000 VON=0.1 VOFF=6 xX_U9 OUT VEE N14860433 VEE FET simulation_lib:VSW_BASIC_GEN:schematic m=1 RON=0.857 ROFF=1000000 VON=6 VOFF=0.1 .ends FET simulation_lib:LM5112:schematic .subckt FET simulation_lib:INVERTER_BASIC_GEN:schematic IN OUT VCC VSS _M=1 VTHRESH=2.5 .ends FET simulation_lib:INVERTER_BASIC_GEN:schematic .subckt FET simulation_lib:NAND3_BASIC_GEN:schematic IN1 IN2 IN3 OUT VCC VSS _M=1 VTHRESH=2.5 .ends FET simulation_lib:NAND3_BASIC_GEN:schematic .subckt FET simulation_lib:UVLO_BASIC_GEN:schematic SUPPLY OUT CN+ CN- _M=1 VTHRESH=2.5 VHYST=0.5 .ends FET simulation_lib:UVLO_BASIC_GEN:schematic .subckt FET simulation_lib:LS_BASIC_GEN:schematic ND+ ND- LS+ LS- _M=1 .ends FET simulation_lib:LS_BASIC_GEN:schematic .subckt FET simulation_lib:VSW_BASIC_GEN:schematic ND1 ND2 CN+ CN- _M=1 RON=1 ROFF='1e+6' VON=3 VOFF=2 .ends FET simulation_lib:VSW_BASIC_GEN:schematic .subckt FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic IN OUT VCC VSS _M=1 VTHRESH=2.5 DELAY='1e-8' CC1 _node4 VSS C=DELAY*1.4 M $.model $W $L RR1 _node3 _node4 1 M $.model $W $L .ends FET simulation_lib:BUF_DELAY_BASIC_GEN:schematic .subckt FET simulation_lib:INPUTHYST_BASIC_GEN:schematic SUPPLY OUT CN+ CN- _M=1 VTHRESH=2.5 VHYST=0.5 .ends FET simulation_lib:INPUTHYST_BASIC_GEN:schematic .subckt FET simulation_lib:cell_1:schematic DDIODE1 _net4 _net17 DIODEM1 m RR2 0 _net17 1 M $.model $W $L RR4 _net17 VDD 200 M $.model $W $L VSRC4 VDD 0 4.2 xX3 _net4 _net4 _net4 _net4 _net4 _net4 DMC1030UFDB_lib:DMC1030UFDB:schematic m=1 xX4 _net16 _net1 _net13 _net15 _net5 _net2 FET simulation_lib:LM5112:schematic m=1 .ends FET simulation_lib:cell_1:schematic .end