/* * main.c */ /******************************************************************************/ /* Legacy Header File */ /* Not recommended for use in new projects. */ /* Please use the msp430.h file or the device specific header file */ /******************************************************************************/ /******************************************************************** * * Standard register and bit definitions for the Texas Instruments * MSP430 microcontroller. * * This file supports assembler and C development for * MSP430x21x2 devices. * * Texas Instruments, Version 1.2 * * Rev. 1.0, Setup * Rev. 1.1, fixed define: TAG_ADC10_1 to 0x08 * Rev. 1.2, Fixed typo in ADC10: SREF3 -> SREF2 * ********************************************************************/ /*----------------------------------------------------------------------------*/ /* PERIPHERAL FILE MAP */ /*----------------------------------------------------------------------------*/ /* External references resolved by a device-specific linker command file */ /************************************************************ * STANDARD BITS ************************************************************/ /************************************************************ * STATUS REGISTER BITS ************************************************************/ /* Low Power Modes coded with Bits 4-7 in SR */ /*----------------------------------------------------------------------------*/ /* in430.h - Intrinsic function prototypes and convenience mapping */ /* macros for migrating code from the IAR platform. */ /* */ /* Ver | dd mmm yyyy | Who | Description of changes */ /* =====|=============|======|============================================= */ /* 0.01| 06 Apr 2004 | A.D. | First Prototype */ /* 0.02| 22 Jun 2004 | A.D. | File reformatted */ /* */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* COMPILER INTRINSIC FUNCTIONS */ /*----------------------------------------------------------------------------*/ void _enable_interrupts(void); void _disable_interrupts(void); unsigned short _bic_SR_register(unsigned short mask); unsigned short _bic_SR_register_on_exit(unsigned short mask); unsigned short _bis_SR_register(unsigned short mask); unsigned short _bis_SR_register_on_exit(unsigned short mask); unsigned short _get_SR_register(void); unsigned short _get_SR_register_on_exit(void); unsigned short _swap_bytes(unsigned short src); void _nop(void); void _never_executed(void); /*----------------------------------------------------------------------------*/ /* INTRINSIC MAPPING FOR IAR V1.XX */ /*----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------*/ /* INTRINSIC MAPPING FOR IAR V2.XX/V3.XX */ /*----------------------------------------------------------------------------*/ /************************************************************ * PERIPHERAL FILE MAP ************************************************************/ /************************************************************ * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS ************************************************************/ extern volatile unsigned char IE1; /* Interrupt Enable 1 */ extern volatile unsigned char IFG1; /* Interrupt Flag 1 */ extern volatile unsigned char IE2; /* Interrupt Enable 2 */ extern volatile unsigned char IFG2; /* Interrupt Flag 2 */ /************************************************************ * ADC10 ************************************************************/ extern volatile unsigned char ADC10DTC0; /* ADC10 Data Transfer Control 0 */ extern volatile unsigned char ADC10DTC1; /* ADC10 Data Transfer Control 1 */ extern volatile unsigned char ADC10AE0; /* ADC10 Analog Enable 0 */ extern volatile unsigned char ADC10AE1; /* ADC10 Analog Enable 1 */ extern volatile unsigned int ADC10CTL0; /* ADC10 Control 0 */ extern volatile unsigned int ADC10CTL1; /* ADC10 Control 1 */ extern volatile unsigned int ADC10MEM; /* ADC10 Memory */ extern volatile unsigned int ADC10SA; /* ADC10 Data Transfer Start Address */ /* ADC10CTL0 */ /* ADC10CTL1 */ /* ADC10DTC0 */ /************************************************************ * Basic Clock Module ************************************************************/ extern volatile unsigned char DCOCTL; /* DCO Clock Frequency Control */ extern volatile unsigned char BCSCTL1; /* Basic Clock System Control 1 */ extern volatile unsigned char BCSCTL2; /* Basic Clock System Control 2 */ extern volatile unsigned char BCSCTL3; /* Basic Clock System Control 3 */ /************************************************************ * Comparator A ************************************************************/ extern volatile unsigned char CACTL1; /* Comparator A Control 1 */ extern volatile unsigned char CACTL2; /* Comparator A Control 2 */ extern volatile unsigned char CAPD; /* Comparator A Port Disable */ /************************************************************* * Flash Memory *************************************************************/ extern volatile unsigned int FCTL1; /* FLASH Control 1 */ extern volatile unsigned int FCTL2; /* FLASH Control 2 */ extern volatile unsigned int FCTL3; /* FLASH Control 3 */ /************************************************************ * DIGITAL I/O Port1/2 Pull up / Pull down Resistors ************************************************************/ extern volatile unsigned char P1IN; /* Port 1 Input */ extern volatile unsigned char P1OUT; /* Port 1 Output */ extern volatile unsigned char P1DIR; /* Port 1 Direction */ extern volatile unsigned char P1IFG; /* Port 1 Interrupt Flag */ extern volatile unsigned char P1IES; /* Port 1 Interrupt Edge Select */ extern volatile unsigned char P1IE; /* Port 1 Interrupt Enable */ extern volatile unsigned char P1SEL; /* Port 1 Selection */ extern volatile unsigned char P1SEL2; /* Port 1 Selection 2 */ extern volatile unsigned char P1REN; /* Port 1 Resistor Enable */ extern volatile unsigned char P2IN; /* Port 2 Input */ extern volatile unsigned char P2OUT; /* Port 2 Output */ extern volatile unsigned char P2DIR; /* Port 2 Direction */ extern volatile unsigned char P2IFG; /* Port 2 Interrupt Flag */ extern volatile unsigned char P2IES; /* Port 2 Interrupt Edge Select */ extern volatile unsigned char P2IE; /* Port 2 Interrupt Enable */ extern volatile unsigned char P2SEL; /* Port 2 Selection */ extern volatile unsigned char P2SEL2; /* Port 2 Selection 2 */ extern volatile unsigned char P2REN; /* Port 2 Resistor Enable */ /************************************************************ * DIGITAL I/O Port3 Pull up / Pull down Resistors ************************************************************/ extern volatile unsigned char P3IN; /* Port 3 Input */ extern volatile unsigned char P3OUT; /* Port 3 Output */ extern volatile unsigned char P3DIR; /* Port 3 Direction */ extern volatile unsigned char P3SEL; /* Port 3 Selection */ extern volatile unsigned char P3REN; /* Port 3 Resistor Enable */ /************************************************************ * Timer0_A3 ************************************************************/ extern volatile unsigned int TA0IV; /* Timer0_A3 Interrupt Vector Word */ extern volatile unsigned int TA0CTL; /* Timer0_A3 Control */ extern volatile unsigned int TA0CCTL0; /* Timer0_A3 Capture/Compare Control 0 */ extern volatile unsigned int TA0CCTL1; /* Timer0_A3 Capture/Compare Control 1 */ extern volatile unsigned int TA0CCTL2; /* Timer0_A3 Capture/Compare Control 2 */ extern volatile unsigned int TA0R; /* Timer0_A3 */ extern volatile unsigned int TA0CCR0; /* Timer0_A3 Capture/Compare 0 */ extern volatile unsigned int TA0CCR1; /* Timer0_A3 Capture/Compare 1 */ extern volatile unsigned int TA0CCR2; /* Timer0_A3 Capture/Compare 2 */ /* Alternate register names */ /* Alternate register names 2 */ /* T0_A3IV Definitions */ /************************************************************ * Timer1_A2 ************************************************************/ extern volatile unsigned int TA1IV; /* Timer1_A5 Interrupt Vector Word */ extern volatile unsigned int TA1CTL; /* Timer1_A5 Control */ extern volatile unsigned int TA1CCTL0; /* Timer1_A5 Capture/Compare Control 0 */ extern volatile unsigned int TA1CCTL1; /* Timer1_A5 Capture/Compare Control 1 */ extern volatile unsigned int TA1R; /* Timer1_A5 */ extern volatile unsigned int TA1CCR0; /* Timer1_A5 Capture/Compare 0 */ extern volatile unsigned int TA1CCR1; /* Timer1_A5 Capture/Compare 1 */ /* Bits are already defined within the Timer0_Ax */ /* T1_A2IV Definitions */ /************************************************************ * USCI ************************************************************/ extern volatile unsigned char UCA0CTL0; /* USCI A0 Control Register 0 */ extern volatile unsigned char UCA0CTL1; /* USCI A0 Control Register 1 */ extern volatile unsigned char UCA0BR0; /* USCI A0 Baud Rate 0 */ extern volatile unsigned char UCA0BR1; /* USCI A0 Baud Rate 1 */ extern volatile unsigned char UCA0MCTL; /* USCI A0 Modulation Control */ extern volatile unsigned char UCA0STAT; /* USCI A0 Status Register */ extern volatile unsigned char UCA0RXBUF; /* USCI A0 Receive Buffer */ extern volatile unsigned char UCA0TXBUF; /* USCI A0 Transmit Buffer */ extern volatile unsigned char UCA0ABCTL; /* USCI A0 LIN Control */ extern volatile unsigned char UCA0IRTCTL; /* USCI A0 IrDA Transmit Control */ extern volatile unsigned char UCA0IRRCTL; /* USCI A0 IrDA Receive Control */ extern volatile unsigned char UCB0CTL0; /* USCI B0 Control Register 0 */ extern volatile unsigned char UCB0CTL1; /* USCI B0 Control Register 1 */ extern volatile unsigned char UCB0BR0; /* USCI B0 Baud Rate 0 */ extern volatile unsigned char UCB0BR1; /* USCI B0 Baud Rate 1 */ extern volatile unsigned char UCB0I2CIE; /* USCI B0 I2C Interrupt Enable Register */ extern volatile unsigned char UCB0STAT; /* USCI B0 Status Register */ extern volatile unsigned char UCB0RXBUF; /* USCI B0 Receive Buffer */ extern volatile unsigned char UCB0TXBUF; /* USCI B0 Transmit Buffer */ extern volatile unsigned int UCB0I2COA; /* USCI B0 I2C Own Address */ extern volatile unsigned int UCB0I2CSA; /* USCI B0 I2C Slave Address */ // UART-Mode Bits // SPI-Mode Bits // I2C-Mode Bits //#define res (0x10) /* reserved */ // UART-Mode Bits // SPI-Mode Bits //#define res (0x20) /* reserved */ //#define res (0x10) /* reserved */ //#define res (0x08) /* reserved */ //#define res (0x04) /* reserved */ //#define res (0x02) /* reserved */ // I2C-Mode Bits //#define res (0x20) /* reserved */ //#define res (0x80) /* reserved */ //#define res (0x40) /* reserved */ //#define res (0x20) /* reserved */ //#define res (0x10) /* reserved */ //#define res (0x80) /* reserved */ //#define res (0x40) /* reserved */ //#define res (0x02) /* reserved */ /************************************************************ * WATCHDOG TIMER ************************************************************/ extern volatile unsigned int WDTCTL; /* Watchdog Timer Control */ /* The bit names have been prefixed with "WDT" */ /* WDT-interval times [1ms] coded with Bits 0-2 */ /* WDT is clocked by fSMCLK (assumed 1MHz) */ /* WDT is clocked by fACLK (assumed 32KHz) */ /* Watchdog mode -> reset after expired time */ /* WDT is clocked by fSMCLK (assumed 1MHz) */ /* WDT is clocked by fACLK (assumed 32KHz) */ /* INTERRUPT CONTROL */ /* These two bits are defined in the Special Function Registers */ /* #define WDTIE 0x01 */ /* #define WDTIFG 0x01 */ /************************************************************ * Calibration Data in Info Mem ************************************************************/ /* TLV Calibration Data Structure */ extern volatile unsigned int TLV_CHECKSUM; /* TLV CHECK SUM */ extern volatile unsigned char TLV_DCO_30_TAG; /* TLV TAG_DCO30 TAG */ extern volatile unsigned char TLV_DCO_30_LEN; /* TLV TAG_DCO30 LEN */ extern volatile unsigned char TLV_ADC10_1_TAG; /* TLV ADC10_1 TAG */ extern volatile unsigned char TLV_ADC10_1_LEN; /* TLV ADC10_1 LEN */ /************************************************************ * Calibration Data in Info Mem ************************************************************/ extern volatile unsigned char CALDCO_16MHZ; /* DCOCTL Calibration Data for 16MHz */ extern volatile unsigned char CALBC1_16MHZ; /* BCSCTL1 Calibration Data for 16MHz */ extern volatile unsigned char CALDCO_12MHZ; /* DCOCTL Calibration Data for 12MHz */ extern volatile unsigned char CALBC1_12MHZ; /* BCSCTL1 Calibration Data for 12MHz */ extern volatile unsigned char CALDCO_8MHZ; /* DCOCTL Calibration Data for 8MHz */ extern volatile unsigned char CALBC1_8MHZ; /* BCSCTL1 Calibration Data for 8MHz */ extern volatile unsigned char CALDCO_1MHZ; /* DCOCTL Calibration Data for 1MHz */ extern volatile unsigned char CALBC1_1MHZ; /* BCSCTL1 Calibration Data for 1MHz */ /************************************************************ * Interrupt Vectors (offset from 0xFFE0) ************************************************************/ /*#define PORT1_ISR(func) ISR_VECTOR(func, ".int02") */ /* 0xFFE4 Port 1 */ /* CCE V2 Style */ /*#define PORT2_ISR(func) ISR_VECTOR(func, ".int03") */ /* 0xFFE6 Port 2 */ /* CCE V2 Style */ /*#define ADC10_ISR(func) ISR_VECTOR(func, ".int05") */ /* 0xFFEA ADC10 */ /* CCE V2 Style */ /*#define USCIAB0TX_ISR(func) ISR_VECTOR(func, ".int06") */ /* 0xFFEC USCI A0/B0 Transmit */ /* CCE V2 Style */ /*#define USCIAB0RX_ISR(func) ISR_VECTOR(func, ".int07") */ /* 0xFFEE USCI A0/B0 Receive */ /* CCE V2 Style */ /*#define TIMER0_A1_ISR(func) ISR_VECTOR(func, ".int08") */ /* 0xFFF0 Timer0 A CC1-2, TA */ /* CCE V2 Style */ /*#define TIMER0_A0_ISR(func) ISR_VECTOR(func, ".int09") */ /* 0xFFF2 Timer0 A CC0 */ /* CCE V2 Style */ /*#define WDT_ISR(func) ISR_VECTOR(func, ".int10") */ /* 0xFFF4 Watchdog Timer */ /* CCE V2 Style */ /*#define COMPARATORA_ISR(func) ISR_VECTOR(func, ".int11") */ /* 0xFFF6 Comparator A */ /* CCE V2 Style */ /*#define TIMER1_A1_ISR(func) ISR_VECTOR(func, ".int12") */ /* 0xFFF8 Timer1 A CC1-2, TA */ /* CCE V2 Style */ /*#define TIMER1_A0_ISR(func) ISR_VECTOR(func, ".int13") */ /* 0xFFFA Timer1 A CC0 */ /* CCE V2 Style */ /*#define NMI_ISR(func) ISR_VECTOR(func, ".int14") */ /* 0xFFFC Non-maskable */ /* CCE V2 Style */ /*#define RESET_ISR(func) ISR_VECTOR(func, ".int15") */ /* 0xFFFE Reset [Highest Priority] */ /* CCE V2 Style */ /************************************************************ * End of Modules ************************************************************/ //States unsigned int State; void main(void) { WDTCTL = (0x5A00) + (0x0080); // Stop Watchdog Timer if ((0x0005) ==0xFF || (0x0004) == 0xFF) // Check for declaraiton of calibrated system frequencies { while(1); // If calibration constants erased, do not load, trap CPU!! } BCSCTL1 = CALBC1_8MHZ; // Set DCO to 8MHz DCOCTL = CALDCO_8MHZ; BCSCTL2 = (0x06); // SMCLk/8 from DCO (1MHz) _bis_SR_register((0x0020)); // Turn off the external oscillator // Configure Timer 1 TA0CCTL0 = (0x0010); // Timer 1 interrupt enabled TA0CCR0 = 10000; // 10000 * 1us = 10ms timer TA0CTL = (2*0x100u) + (1*0x10u); // configure Timer 1 from SMCLK, upmode State = 0x00; WDTCTL = ((0x5A00)+(0x0008)); // Enable Watchdog on 32ms time out if (!(_get_SR_register() & 0x0008)) {_bis_SR_register((0x0008));} // Check interupt status and enable for(;;) {} // Trap forever, wait for ISR } // Timer0_A0 interrupt service routine #pragma vector=(9 * 1u) __interrupt void Timer_A (void) { /*switch(State) // Go to operating state { case OFF: { __delay_cycles(1000); //Off_State(); }break; case ENABLE_FETS: { __delay_cycles(1000); //Enable_Fets_State(); }break; case PWM_START: { __delay_cycles(1000); //PWM_Start_State(); }break; case OP_CHECK: { __delay_cycles(1000); //OP_Check_State(); }break; case RUN: { __delay_cycles(1000); //Run_State(); }break; case SHUTDOWN: { __delay_cycles(1000); //Shutdown_State(); }break; case RESTART: { __delay_cycles(1000); //Restart_State(); }break; default: _never_executed(); }*/ //Alternative switch statement method switch(__even_in_range(State,0x0C)) { case 0x00: { __delay_cycles(1000); //Off_State(); }break; case 0x02: { __delay_cycles(1000); //Enable_Fets_State(); }break; case 0x04: { __delay_cycles(1000); //PWM_Start_State(); }break; case 0x06: { __delay_cycles(1000); //OP_Check_State(); }break; case 0x08: { __delay_cycles(1000); //Run_State(); }break; case 0x0A: { __delay_cycles(1000); //Shutdown_State(); }break; case 0x0C: { __delay_cycles(1000); //Restart_State(); }break; } WDTCTL = (0x5A00) + (0x0008); // Reset the 16mS watchdog Timer. }