SECTIONS { ISR_vectors: > VECS .cinit: > PSRAM0 //.text: > PSRAM1 // commented this to see if what u explained works isrs: > PSRAM0 .switch: > PSRAM0 .const: > DSRAM0 .stack: > DSRAM0|DSRAM1 .sysstack: > DSRAM0|DSRAM1 .sysmem: > DSRAM0|DSRAM1 .data: > DSRAM0|DSRAM1 .bss: > DSRAM0|DSRAM1 // .const1 {MelpE_adt.l55l (.const)} > SARAM1 PAGE 0 BufLog: { .\Debug\buflog.obj (.bss)} >DSRAM1 // btext: > PSRAM0 // commented this to see if what u explained works vtext: { libmesi.a55 (.text) /* apsk.obj (.text) aeq.obj (.text) interp.obj (.text)*/ libmesi.a55 (.text) libmesi.a55 (.text) libmesi.a55 (.text) libmesi.a55 (.text) libmesi.a55 (.text) libmesi.a55 (.text) libmesi.a55 (.text) libmesi.a55 < v17.obj> (.text) libmesi.a55 < relay.obj> (.text) libmesi.a55 < sequence.obj> (.text) libmesi.a55 < fsk.obj> (.text) libmesi.a55 < bufmgr.obj> (.text) libmesi.a55 < rxtx.obj> (.text) libmesi.a55 < hdlc.obj> (.text) buflog.obj (.text) libmesi.a55 (.text) libmesi.a55 < packdata.obj> (.text) libmesi.a55 < netif.obj> (.text) libmesi.a55 (.text) libmesi.a55 (.text) libmesi.a55 (.text) } > PSRAM0|PSRAM1 vcoefs: { // libmesi.a55< vcoefs.obj> (.const) //libmesi.a55 (.const) //libmesi.a55 (.const) //libmesi.a55 (.const) // libmesi.a55 (.const) libmesi.a55 (.const) libmesi.a55 < modemif.obj> (.const) libmesi.a55 < t38.obj> (.const) } > DSRAM0|PSRAM0 vdata: { .\Debug\faxmem.obj (.bss) // added a realtive path to find the file } > DSRAM0 dumper: > DSRAM1 }